LT1766_1 datasheet(19/30 Pages) LINER

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LT1766/LT1766-5

1766fc

APPLICATIONS INFORMATION

maximum rating. A ground plane should always be used

under the switcher circuitry to prevent interplane coupling

and overall noise.

The VC and FB components should be kept as far away as

possible from the switch and boost nodes. The LT1766

pinout has been designed to aid in this. The ground for

these components should be separated from the switch

current path. Failure to do so will result in poor stability

or subharmonic like oscillation.

Board layout also has a signiﬁcant effect on thermal

resistance. Pins 1, 8, 9 and 16, GND, are a continuous

copper plate that runs under the LT1766 die. This is the

best thermal path for heat out of the package. Reducing

the thermal resistance from Pins 1, 8, 9 and 16 onto the

board will reduce die temperature and increase the power

capability of the LT1766. This is achieved by providing as

much copper area as possible around these pins. Add-

ing multiple solder ﬁlled feedthroughs under and around

these four corner pins to the ground plane will also help.

Similar treatment to the catch diode and coil terminations

will reduce any additional heating effects. For the FE pack-

age, the exposed pad (Pin 17) should be soldered to the

copper ground plane underneath the device.

PARASITIC RESONANCE

Resonance or ringing may sometimes be seen on the

switch node (see Figure 7). Very high frequency ringing

following switch rise time is caused by switch/diode/input

capacitor lead inductance and diode capacitance. Schottky

diodes have very high “Q” junction capacitance that can

ring for many cycles when excited at high frequency. If

total lead length for the input capacitor, diode and switch

path is 1 inch, the inductance will be approximately 25nH.

At switch off, this will produce a spike across the NPN

output device in addition to the input voltage. At higher

currents this spike can be in the order of 10V to 20V

or higher with a poor layout, potentially exceeding the

absolute max switch voltage. The path around switch,

catch diode and input capacitor must be kept as short as

possible to ensure reliable operation. When looking at this,

Figure 6. Suggested Layout

GND

SHDN

SYNC

GND

BOOST

VIN

PLACE FEEDTHROUGH AROUND

GROUND PINS (4 CORNERS) FOR

GOOD THERMAL CONDUCTIVITY

LT1766

1766 F06

CFB

MINIMIZE LT1766

C3-D1 LOOP

GND

BIAS

CONNECT TO

GROUND PLANE

KELVIN SENSE

VOUT

KEEP FB AND VC COMPONENTS

AWAY FROM HIGH FREQUENCY,

HIGH CURRENT COMPONENTS

FOR THE FE PACKAGE, THE

EXPOSED PAD (PIN 17) SHOULD

BE PROPERLY SOLDERED TO

THE GROUND PLANE.

NOTE: BOOST AND BIAS

COPPER TRACES ARE ON

A SEPARATE LAYER FROM

THE GROUND PLANE

GND

VOUT

VIN

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