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Output Phase Reversal

Sampling Mode

Power-Down Modes

Software Reset

Audio Data Formats, LRCK Polarity, and BCK Sampling Edge

SERIAL PERIPHERAL INTERFACE (SPI) PORT OPERATION

Control Byte (or Byte 0)

PCM4104-EP

SBAS419 – JUNE 2007

The PCM4104 includes an output phase reversal function, which provides the ability to invert the output phase

for all four channels, either for testing or for matching various output circuit configurations. This function is

controlled using the PHASE bit, located within Control Register 5. The output phase is set to noninverted by

default on power up or reset.

Sampling mode configuration was discussed earlier in this data sheet, with Table 1 providing a reference for

common sampling and system clock frequencies. The FS0 and FS1 bits located in Control Register 6 are used

to set the sampling mode. The sampling mode defaults to Single Rate on power up or reset.

The power-down control bits are located in Control Register 6. These bits are used to power down pairs of D/A

converters within the PCM4104. The PDN12 bit is used to power down channels 1 and 2, while the PDN34 bit is

used to power down channels 3 and 4. When a channel pair is powered down, it ignores the audio data inputs

and sets its outputs to a high-impedance state. By default, the power-down bits are disabled on power up or

reset.

This reset function allows a reset sequence to be initiated under software control. All control registers are reset

to their default state. The reset bit, RST, is located in Control Register 6. Setting this bit to 1 initiates a one-time

reset sequence. The RST bit is cleared by the initialization sequence.

Control Register 7 is used to configure the PCM4104 audio serial port. Audio serial port operation was

discussed previously in this data sheet; refer to that section for more details regarding the functions controlled by

this register. The control register definitions provide additional information regarding the register functions and

their default settings.

The SPI port is a four-wire synchronous serial interface that is used to access the on-chip control registers when

the PCM4104 is configured for Software mode operation. The CDIN input (pin 23) is the serial data input for the

port, while CDOUT (pin 24) is used for reading back control register contents in a serial fashion. The CS input

(pin 21) functions as the chip select input, and must be forced low for register write or read access. The CCLK

input (pin 22) functions as the serial data clock, used to clock data in and out of the port. Data is clocked into the

port on the rising edge of CCLK, while data is clocked out of the port on the falling edge of CCLK.

There are three modes of operation supported for the SPI port: Single Register, Continuous, and

Auto-Increment.

The Single Register and Continuous modes are similar to one another. In Continuous mode, instead of bringing

the CS input high after writing or reading a single register, the CS input is held low and a new control byte is

issued with a new address for the next write or read operation. Continuous mode allows multiple, sequential or

nonsequential register addresses to be read or written in succession, as shown in Figure 16.

Auto-Increment mode is designed for writing or reading multiple sequential register addresses. After the first

register is written or read, the register address is automatically incremented by 1, so the next write or read

operation is performed without issuing another control byte, as shown in Figure 17.

The control byte, or byte 0, is the first byte written to the PCM4104 SPI port when performing a write or read

operation. The control byte includes bits that define the operation to be performed (read or write), the

auto-increment mode status, and the control register address.

The Read/Write bit, R/W, is set to 0 to indicate a register write operation, or set to 1 for a register read

operation.

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