PIC18F4580-ESLASHML datasheet(135/490 Pages) MICROCHIP

135 / 490 page

DS39637D-page 135

PIC18F2480/2580/4480/4580

11.0 I/O PORTS

Depending on the device selected and features

enabled, there are up to five ports available. Some pins

of the I/O ports are multiplexed with an alternate

function from the peripheral features on the device. In

general, when a peripheral is enabled, that pin may not

be used as a general purpose I/O pin.

Each port has three registers for its operation. These

registers are:

• TRIS register (Data Direction register)

• PORT register (reads the levels on the pins of the

device)

• LAT register (Output Latch register)

The Output Latch register (LAT) is useful for read-

modify-write operations on the value that the I/O pins

are driving.

A simplified model of a generic I/O port, without the

interfaces to other peripherals, is shown in Figure 11-1.

FIGURE 11-1:

GENERIC I/O PORT

OPERATION

11.1

PORTA, TRISA and LATA Registers

PORTA is an 8-bit wide, bidirectional port. The

corresponding Data Direction register is TRISA. Setting

a TRISA bit (= 1) will make the corresponding PORTA

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISA bit (= 0)

will make the corresponding PORTA pin an output (i.e.,

put the contents of the Output Latch register on the

selected pin).

Reading the PORTA register reads the status of the

pins, whereas writing to it, will write to the port latch.

The Output Latch register (LATA) is also memory

mapped. Read-modify-write operations on the LATA

PORTA.

The RA4 pin is multiplexed with the Timer0 module

clock input to become the RA4/T0CKI pin. Pins, RA6

and RA7, are multiplexed with the main oscillator pins;

they are enabled as oscillator or I/O pins by the selec-

tion of the main oscillator in Configuration Register 1H

(see Section 25.1 “Configuration Bits” for details).

When they are not used as port pins, RA6 and RA7 and

their associated TRIS and LAT bits are read as ‘0’.

The other PORTA pins are multiplexed with analog

inputs, the analog VREF+ and VREF- inputs and the

comparator voltage reference output. The operation of

pins, RA<3:0> and RA5 as A/D Converter inputs, is

selected by clearing/setting the control bits in the

ADCON1 register (A/D Control Register 1).

All other PORTA pins have TTL input levels and full

CMOS output drivers.

The TRISA register controls the direction of the RA

pins, even when they are being used as analog inputs.

The user must ensure the bits in the TRISA register are

maintained set when using them as analog inputs.

EXAMPLE 11-1:

INITIALIZING PORTA

Data

Bus

WR LAT

WR TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Input

Buffer

I/O pin(1)

RD LAT

or PORT

Note 1:

I/O pins have diode protection to VDD and VSS.

Note:

On a Power-on Reset, RA5 and RA<3:0>

are configured as analog inputs and read

as ‘0’. RA4 is configured as a digital input.

CLRF

PORTA

; Initialize PORTA by

; clearing output

; data latches

CLRF

LATA

; Alternate method

; to clear output

; data latches

MOVLW

0Fh

; Configure A/D

MOVWF

ADCON1 ; for digital inputs

MOVWF

07h

; Configure comparators

MOVWF

CMCON

; for digital input

MOVLW

0CFh

; Value used to

; initialize data

; direction

MOVWF

TRISA

; Set RA<3:0> as inputs

; RA<5:4> as outputs

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