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PIC16F1824-E/ML датащи(PDF) 96 Page - Microchip Technology

номер детали PIC16F1824-E/ML
подробное описание детали  14/20-Pin Flash Microcontrollers with nanoWatt XLP Technology
PDF  420 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16F1824-E/ML датащи(HTML) 96 Page - Microchip Technology

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PIC16F/LF1824/1828
DS41419A-page 96
Preliminary
 2010 Microchip Technology Inc.
8.5.4
PIE3 REGISTER
The PIE3 register contains the interrupt enable bits, as
shown in Register 8-4.
Note 1: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 8-4:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
U-0
—
—
CCP4IE
CCP3IE
TMR6IE
—TMR4IE
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5
CCP4IE: CCP4 Interrupt Enable bit
1 = Enables the CCP4 interrupt
0 = Disables the CCP4 interrupt
bit 4
CCP3IE: CCP3 Interrupt Enable bit
1 = Enables the CCP3 interrupt
0 = Disables the CCP3 interrupt
bit 3
TMR6IE: TMR6 to PR6 Match Interrupt Enable bit
1 = Enables the TMR6 to PR6 Match interrupt
0 = Disables the TMR6 to PR6 Match interrupt
bit 2
Unimplemented: Read as ‘0’
bit 1
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enables the TMR4 to PR4 Match interrupt
0 = Disables the TMR4 to PR4 Match interrupt
bit 0
Unimplemented: Read as ‘0’



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