PIC16F1824-ESLASHML datasheet(92/420 Pages) MICROCHIP

92 / 420 page

PIC16F/LF1824/1828

DS41419A-page 92

Preliminary

 2010 Microchip Technology Inc.

8.3

Interrupts During Sleep

Some interrupts can be used to wake from Sleep. To

wake from Sleep, the peripheral must be able to

operate without the system clock. The interrupt source

must have the appropriate Interrupt Enable bit(s) set

prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the

processor will branch to the interrupt vector. Otherwise,

the processor will continue executing instructions after

the SLEEP instruction. The instruction directly after the

SLEEP instruction will always be executed before

branching to the ISR. Refer to the Section 9.0 “Power-

Down Mode (Sleep)” for more details.

8.4

INT Pin

The INT pin can be used to generate an asynchronous

edge-triggered interrupt. This interrupt is enabled by

setting the INTE bit of the INTCON register. The

INTEDG bit of the OPTION register determines on which

edge the interrupt will occur. When the INTEDG bit is

set, the rising edge will cause the interrupt. When the

INTEDG bit is clear, the falling edge will cause the

interrupt. The INTF bit of the INTCON register will be set

when a valid edge appears on the INT pin. If the GIE and

INTE bits are also set, the processor will redirect

program execution to the interrupt vector.

8.5

Automatic Context Saving

Upon entering an interrupt, the return PC address is

saved on the stack. Additionally, the following registers

are automatically saved in the Shadow registers:

• W register

• STATUS register (except for TO and PD)

• BSR register

• FSR registers

• PCLATH register

Upon exiting the Interrupt Service Routine, these regis-

ters are automatically restored. Any modifications to

these registers during the ISR will be lost. If modifica-

tions to any of these registers are desired, the corre-

sponding Shadow register should be modified and the

value will be restored when exiting the ISR. The

Shadow registers are available in Bank 31 and are

readable and writable. Depending on the user’s appli-

cation, other registers may also need to be saved.

PIC16F1824-E/ML датащи(PDF) 92 Page - Microchip Technology

PIC16F1824-E/ML датащи(HTML) 92 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL