PIC12F1822-ISLASHMF datasheet(261/398 Pages) MICROCHIP

261 / 398 page

 2010 Microchip Technology Inc.

Preliminary

DS41413A-page 261

PIC12F/LF1822/16F/LF1823

24.6.6

I2C MASTER MODE TRANSMISSION

Transmission of a data byte, a 7-bit address or the

other half of a 10-bit address is accomplished by simply

writing a value to the SSP1BUF register. This action will

set the Buffer Full flag bit, BF, and allow the Baud Rate

Generator to begin counting and start the next trans-

mission. Each bit of address/data will be shifted out

onto the SDA pin after the falling edge of SCL is

asserted. SCL is held low for one Baud Rate Generator

rollover count (TBRG). Data should be valid before SCL

is released high. When the SCL pin is released high, it

is held that way for TBRG. The data on the SDA pin

must remain stable for that duration and some hold

time after the next falling edge of SCL. After the eighth

bit is shifted out (the falling edge of the eighth clock),

the BF flag is cleared and the master releases SDA.

This allows the slave device being addressed to

respond with an ACK bit during the ninth bit time if an

address match occurred, or if data was received prop-

erly. The status of ACK is written into the ACKSTAT bit

on the rising edge of the ninth clock. If the master

receives an Acknowledge, the Acknowledge Status bit,

ACKSTAT, is cleared. If not, the bit is set. After the ninth

clock, the SSP1IF bit is set and the master clock (Baud

Rate Generator) is suspended until the next data byte

is loaded into the SSP1BUF, leaving SCL low and SDA

unchanged (Figure 24-27).

After the write to the SSP1BUF, each bit of the address

will be shifted out on the falling edge of SCL until all

seven address bits and the R/W bit are completed. On

the falling edge of the eighth clock, the master will

release the SDA pin, allowing the slave to respond with

an Acknowledge. On the falling edge of the ninth clock,

the master will sample the SDA pin to see if the address

was recognized by a slave. The status of the ACK bit is

loaded into the ACKSTAT Status bit of the SSP1CON2

transmission of the address, the SSP1IF is set, the BF

flag is cleared and the Baud Rate Generator is turned

off until another write to the SSP1BUF takes place,

holding SCL low and allowing SDA to float.

24.6.6.1

BF Status Flag

In Transmit mode, the BF bit of the SSP1STAT register

is set when the CPU writes to SSP1BUF and is cleared

when all 8 bits are shifted out.

24.6.6.2

WCOL Status Flag

If the user writes the SSP1BUF when a transmit is

already in progress (i.e., SSP1SR is still shifting out a

data byte), the WCOL is set and the contents of the buf-

fer are unchanged (the write doesn’t occur).

WCOL must be cleared by software before the next

transmission.

24.6.6.3

ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit of the SSP1CON2

edge (ACK = 0) and is set when the slave does not

Acknowledge (ACK = 1). A slave sends an Acknowl-

edge when it has recognized its address (including a

general call), or when the slave has properly received

its data.

24.6.6.4

Typical transmit sequence:

The user generates a Start condition by setting

the SEN bit of the SSP1CON2 register.

SSP1IF is set by hardware on completion of the

Start.

SSP1IF is cleared by software.

The MSSP1 module will wait the required start

time before any other operation takes place.

The user loads the SSP1BUF with the slave

address to transmit.

Address is shifted out the SDA pin until all 8 bits

are transmitted. Transmission begins as soon

as SSP1BUF is written to.

The MSSP1 module shifts in the ACK bit from

the slave device and writes its value into the

ACKSTAT bit of the SSP1CON2 register.

The MSSP1 module generates an interrupt at

the end of the ninth clock cycle by setting the

SSP1IF bit.

The user loads the SSP1BUF with eight bits of

data.

10. Data is shifted out the SDA pin until all 8 bits are

transmitted.

11. The MSSP1 module shifts in the ACK bit from

the slave device and writes its value into the

ACKSTAT bit of the SSP1CON2 register.

12. Steps 8-11 are repeated for all transmitted data

bytes.

13. The user generates a Stop or Restart condition

by setting the PEN or RSEN bits of the

SSP1CON2 register. Interrupt is generated

once the Stop/Restart condition is complete.

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