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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC12F1822-I/MF датащи(PDF) 258 Page - Microchip Technology |
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PIC12F1822-I/MF датащи(HTML) 258 Page - Microchip Technology |
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258 / 398 page  PIC12F/LF1822/16F/LF1823 DS41413A-page 258 Preliminary 2010 Microchip Technology Inc. 24.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Gen- erator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sam- pled high, the Baud Rate Generator is reloaded with the contents of SSP1ADD<7:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 24-25). FIGURE 24-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION 24.6.3 WCOL STATUS FLAG If the user writes the SSP1BUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). Any time the WCOL bit is set it indicates that an action on SSP1BUF was attempted while the module was not Idle. SDA SCL SCL deasserted but slave holds DX ‚ – 1 DX BRG SCL is sampled high, reload takes place and BRG starts its count 03h 02h 01h 00h (hold off) 03h 02h Reload BRG Value SCL low (clock arbitration) SCL allowed to transition high BRG decrements on Q2 and Q4 cycles Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSP1CON2 is disabled until the Start condition is complete. |
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