TX _ CLK

TX _ DATA 15 - 0

TX _ DATAK

1 - 0

Valid Data

Thd 2

Tcyc 2

Tsu 2

PCLK

RX _ DATA

15 - 0

RX _ DATAK

1 - 0

RX _ VALID

RX _STATUS

2 - 0

PHY _ STATUS

Valid Data

Tcyc 3

Tdly 3

TUSB1310

SLLSE16B – DECEMBER 2009 – REVISED JUNE 2010

www.ti.com

6.4.2

PIPE Transmit

Figure 6-2. PIPE Transmit Timing

Table 6-2. PIPE Transmit Timing

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNIT

Tcyc2

TX_CLK Period

4

ns

Tdty2

TX_CLK Period

50

%

Tsu2

1

ns

Thd2

0

ns

(1)

This includes TX_DATA15-0, TX_DATAK1-0, TX_ONESZEROS, RATE, TX_DEEMPTH, TX_DETRX_LPBK, TX_ELECIDLE,

TX_MARGIN, TX_SWING, RX_POLARITY, POWER_DOWN1-0.

6.4.3

PIPE Receive

Figure 6-3. PIPE Receive Timing

Table 6-3. PIPE Receive Timing

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNIT

Tcyc3

PCLK Period

4

ns

Tdty3

PCLK Duty Cycle

50

%

PCLK rise and fall to RX_DATA15-0, RX_DATAK1-0, RX_VALID,

Tdly3

1

2

ns

(1)

Output Load max = 10 pF, min = 5 pF

(2)

32

ELECTRICAL SPECIFICATIONS

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