TUSB1310

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SLLSE16B – DECEMBER 2009 – REVISED JUNE 2010

3.2

Clocks

3.2.1

Clock Distribution

A source clock should be provided via XI/XO from an external crystal or from a square wave clock. The

USB3.0 PLL provides a clock to the PIPE which drives 250 MHz. The USB2.0 PLL provides a 60-MHz

clock to the ULPI.

3.2.2

Output Clock

The CLKOUT is used by the link layer controller or the MAC. When ClkoutEn bit at the ULPI SS USB

register is set low, a 120-MHz clock is available via the CLKOUT only in the USB U3 power state. If the

ClkoutEn bit is set high, the 250-MHz clock is driven via CLKOUT in all power states.

3.3

Power Management

The SuperSpeed USB power state transition is controlled by the PIPE POWER_DOWN1-0 and the

non-SuperSpeed USB power state is transitioned by setting suspendM bit in the ULPI Function control

register via the ULPI or by asserting the ULPI_STP.

3.3.1

USB Power Management

The USB 3.0 specification improves power consumption by defining 4 power states, U0, U1, U2, and U3

while the PIPE specification defines P0, P1, P2 and P3. The POWER_DOWN pin states are mapped to

LTSSM states as described in Table 2-10. For all power state transitions, the link layer controller must not

begin any operational sequences or further power state transitions until the TUSB1310 has indicated that

the internal state transition is completed.

Table 3-2. Power States

PIPE

USB POWER

POWER

PCLK

PLL

TRANSMITTING

RECEIVING

PHY_STATUS

STATE

STATE

U0, all other LTSSM

A single cycle

P0

On

On

Active or Idle or LFPS

Active or Idle

states

assertion

A single cycle

P1

U1

On

On

Idle or LFPS

Idle

assertion

U2, RxDetect,

A single cycle

P2

On

On

Idle or LFPS or RxDetect

Idle

SS.Inactive

assertion

PHY_STATUS is

Off. The

asserted before

PIPE is in

PCLK is turned off

P3

U3, SS.disabled

an

Off

LFPS or RxDetect

Idle

and deasserted

asynchrono

when PCLK is fully

us mode

off.

When the link layer controller wants to transmit LFPS in P1, P2, or P3 state, it must de-assert

TX_ELECIDLE. The TUSB1310 generates valid LFPS until the TX_ELECIDLE is asserted. The link layer

controller must assert TX_ELECIDLE before transitioning to P0.

When RX_ELECIDLE is de-asserted in P0, P1, P2, or P3, the TUSB1310 receiver monitors for LFPS

except during reset or when RX_TERMINATION is removed for electrical idle.

When the TUSB1310 is in P0 and is actively transmitting; only RX_POLARITY can be asserted.

Copyright © 2009–2010, Texas Instruments Incorporated

FUNCTIONAL DESCRIPTION

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Product Folder Link(s): TUSB1310