Power Supplies

XI

RESETN

PCLK

ULPI_CLK

Internal resetn/

PLL_EN/

SUSPENDM

Internal latched

strapping pin states

Latched data

PHY_STATUS/

ULPI_DIR

300ms

TUSB1310

SLLSE16B – DECEMBER 2009 – REVISED JUNE 2010

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3.1.2

ULPI Reset – Software Reset

After power-up, the link layer controller must set the Reset bit in ULPI register. It resets the core but does

not reset the ULPI interface or the ULPI registers.

During the ULPI reset, the ULPI_DIR is de-asserted. After the reset, the ULPI_DIR is asserted again and

the TUSB1310 sends an RX CMD update to the link layer. During the reset, the link should ignore signals

on the ULPI_DATA7-0 and must not access the TUSB1310.

3.1.3

OUT_ENABLE - Output Enable

Digital IO buffers use two power supplies, core VDD1P1 and IO VDD1P8. During power up,

OUT_ENABLE must be asserted low for proper operation.

3.1.4

Power Up Sequence

The power up sequence is shown in Figure 3-1.

Figure 3-1. Power Up Sequence

After proper power supply sequencing, the reference clock on XI starts to operate. On the RESETN

de-assertion, REFCLKSEL1-0 is determined depending on the PHY_MODE pins, PLL is locked and the

valid ULPI_CLK and the valid PCLK are driven.

After all stable clocks are provided, the TUSB1310 allows the link layer controller to access by

de-asserting the ULPI_DIR. The link layer controller sets the Reset bit in the ULPI register. At the PIPE

in-terface, the PHY_STATUS changes from high to low in order to indicate the TUSB1310 is in the power

state specified by the POWER_DOWN signal. After the PHY_STATUS change, the TUSB1310 is ready

for PIPE transactions.

18

FUNCTIONAL DESCRIPTION

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