SC68C752B datasheet(8/48 Pages) NXP

8 / 48 page

SC68C752B_4

Product data sheet

Rev. 04 — 20 January 2010

8 of 48

NXP Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

If both auto-CTS and auto-RTS are enabled, when RTSn is connected to CTSn, data

transmission does not occur unless the receive FIFO has empty space. Thus, overrun

errors are eliminated during hardware flow control. If not enabled, overrun errors occur if

the transmit data rate exceeds the receive FIFO servicing latency.

6.2.1 Auto-RTS

Auto-RTS data flow control originates in the receiver block (see Figure 1 “Block diagram

of SC68C752B” on page 3). Figure 5 shows RTSn functional timing. The receiver FIFO

trigger levels used in auto-RTS are stored in the TCR. RTSn is active if the receiver FIFO

level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is

reached, RTSn is de-asserted. The sending device (for example, another UART) may

send an additional byte after the trigger level is reached (assuming the sending UART has

another byte to send) because it may not recognize the de-assertion of RTSn until it has

begun sending the additional byte. RTSn is automatically reasserted once the receiver

FIFO reaches the resume trigger level programmed via TCR[7:4]. This re-assertion allows

the sending device to resume transmission.

Fig 4.

Auto flow control (auto-RTS and auto-CTS) example

RECEIVE

FIFO

FLOW

CONTROL

TRANSMIT

FIFO

PARALLEL

TO SERIAL

TRANSMIT

FIFO

RECEIVE

FIFO

UART 1

UART 2

D7 to D0

RXn

TXn

RTSn

CTSn

TXn

RXn

CTSn

RTSn

D7 to D0

002aaf090

SERIAL TO

PARALLEL

SERIAL TO

PARALLEL

FLOW

CONTROL

FLOW

CONTROL

FLOW

CONTROL

PARALLEL

TO SERIAL

N = receiver FIFO trigger level.

The two blocks in dashed lines cover the case where an additional byte is sent, as described in Section 6.2.1.

Fig 5.

RTSn functional timing

Start

byte N

Start

byte N + 1

Start

Stop

RXn

RTSn

R/W

N + 1

002aab086

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