SC68C752B_4

© NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 04 — 20 January 2010

7 of 48

NXP Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

[1]

HVQFN32 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply

ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be

soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias

need to be incorporated in the PCB in the thermal pad region.

6.

Functional description

The UART will perform serial-to-parallel conversion on data characters received from

peripheral devices or modems, and parallel-to-parallel conversion on data characters

transmitted by the processor. The complete status of each channel of the SC68C752B

UART can be read at any time during functional operation by the processor.

The SC68C752B can be placed in an alternate mode (FIFO mode) relieving the processor

of excessive software overhead by buffering received/transmitted characters. Both the

receiver and transmitter FIFOs can store up to 64 bytes (including three additional bits of

error status per byte for the receiver FIFO) and have selectable or programmable trigger

levels. Primary outputs RXRDYn and TXRDYn allow signalling of DMA transfers.

The SC68C752B has selectable hardware flow control and software flow control.

Hardware flow control significantly reduces software overhead and increases system

efficiency by automatically controlling serial data flow using the RTSn output and CTSn

input signals. Software flow control automatically controls data flow by using

programmable Xon/Xoff characters.

The UART includes a programmable baud rate generator that can divide the timing

− 1).

6.1 Trigger levels

The SC68C752B provides independent selectable and programmable trigger levels for

both receiver and transmitter DMA and interrupt generation. After reset, both transmitter

and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of

one byte. The selectable trigger levels are available via the FCR. The programmable

trigger levels are available via the Trigger Level Register (TLR).

6.2 Hardware flow control

Hardware flow control is comprised of auto-CTS and auto-RTS. Auto-CTS and auto-RTS

can be enabled/disabled independently by programming EFR[7:6].

With auto-CTS, CTSn must be active before the UART can transmit data.

Auto-RTS only activates the RTSn output when there is enough room in the FIFO to

receive data and de-activates the RTSn output when the receive FIFO is sufficiently full.

The halt and resume trigger levels in the TCR determine the levels at which RTSn is

activated/deactivated.

Table 3.

Channel selection using CS pin

CS

A3

UART channel

1

-

none

0

0

channel A

0

1

channel B