SC16C751B_2

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 02 — 10 October 2008

12 of 32

NXP Semiconductors

SC16C751B

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

7.1 Transmit and Receive Holding Registers (THR and RHR)

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the

THR, providing that the THR or TSR is empty. The THR empty flag in the LSR register will

be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR.

Note that a write operation can be performed when the THR empty flag is set

(logic 0 = FIFO full; logic 1 = at least one FIFO location available).

The serial receive section also contains an 8-bit Receive Holding Register (RHR).

Receive data is removed from the SC16C751B and receive FIFO by reading the RHR

register. The receive section provides a mechanism to prevent false starts. On the falling

edge of a start or false start bit, an internal receiver counter starts counting clocks at the

16

start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated.

Evaluating the start bit in this manner prevents the receiver from assembling a false

character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter

empty, line status and modem status registers. These interrupts would normally be seen

on the INT output pin.

Table 7.

Interrupt Enable Register bits description

Bit

Symbol

Description

7:6

IER[7:6]

Not used.

5

IER[5]

Low power mode.

logic 0 = disable Low power mode (normal default condition)

logic 1 = enable Low power mode

4

IER[4]

Sleep mode.

logic 0 = disable Sleep mode (normal default condition)

logic 1 = enable Sleep mode. See Section 6.7 “Sleep mode” for details.

3

IER[3]

Modem Status Interrupt.

logic 0 = disable the modem status register interrupt (normal default condition)

logic 1 = enable the modem status register interrupt

2

IER[2]

Receive Line Status interrupt. This interrupt will be issued whenever a fully

assembled receive character is transferred from RSR to the RHR/FIFO, i.e., data

ready, LSR[0].

logic 0 = disable the receiver line status interrupt (normal default condition)

logic 1 = enable the receiver line status interrupt

1

IER[1]

Transmit Holding Register interrupt. This interrupt will be issued whenever the

THR is empty, and is associated with LSR[1].

logic 0 = disable the transmitter empty interrupt (normal default condition)

logic 1 = enable the transmitter empty interrupt