SC16C751B_2

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 02 — 10 October 2008

11 of 32

NXP Semiconductors

SC16C751B

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

7.

Register descriptions

Table 6 details the assigned bit functions for the fifteen SC16C751B internal registers. The

assigned bit functions are more fully defined in Section 7.1 through Section 7.10.

[1]

The value shown represents the register’s initialized hex value; X = n/a.

[2]

These registers are accessible only when LCR[7] = 0.

[3]

Do not write a logic 1 to the reserved bits. Read of the reserved bits reflect unknown values.

[4]

The ‘Special register set’ is accessible only when LCR[7] is set to a logic 1.

Table 6.

SC16C751B internal registers

A2

A1

A0

Register Default[1] Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

General register set[2]

0

0

0

RHR

XX

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0

0

0

THR

XX

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0

0

1

IER

00

0

0

Low

power

mode

Sleep

mode

modem

status

interrupt

receive

line

status

interrupt

transmit

holding

register

receive

holding

register

0

1

0

FCR

00

RCVR

trigger

(MSB)

RCVR

trigger

(LSB)

64-byte

FIFO

enable

reserved

[3]

reserved

[3]

XMIT

FIFO

reset

RCVR

FIFO

reset

FIFO

enable

0

1

0

ISR

01

FIFOs

enabled

FIFOs

enabled

64-byte

FIFO

enable

0

INT

priority

bit 2

INT

priority

bit 1

INT

priority

bit 0

INT

status

0

1

1

LCR

00

divisor

latch

enable

set break set

parity

even

parity

parity

enable

stop bits

word

length

bit 1

word

length

bit 0

1

0

0

MCR

00

0

0

flow

control

enable

loopback

reserved

[3]

reserved

[3]

RTS

reserved

[3]

1

0

1

LSR

60

FIFO

data

error

trans.

empty

trans.

holding

empty

break

interrupt

framing

error

parity

error

overrun

error

receive

data

ready

1

1

0

MSR

X0

reserved

reserved

reserved CTS

reserved reserved reserved

∆CTS

1

1

1

SPR

FF

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Special register set[4]

0

0

0

DLL

XX

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0

0

1

DLM

XX

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8