PCA9541APWSLASH03 datasheet(11/41 Pages) NXP

11 / 41 page

PCA9541A_3

Product data sheet

Rev. 03 — 16 July 2009

11 of 41

NXP Semiconductors

PCA9541A

2-to-1 I2C-bus master selector with interrupt logic and reset

[1]

Default values are the same for PCA9541A/01, PCA9541A/03.

8.3.2 Register 1: Control Register (B1:B0 = 01b)

The Control Register described below is identical for both the masters. Nevertheless,

there are physically 2 internal Control Registers, one for each upstream channel. When

master 0 reads/writes in this register, the internal Control Register 0 will be accessed.

When master 1 reads/writes in this register, the internal Control Register 1 will be

accessed.

[1]

Default values are the same for PCA9541A/01, PCA9541A/03.

BUSINITMSK

R/W

After connection is requested and Bus Initialization requested (BUSINIT = 1),

an interrupt on INT will be generated when the bus initialization is done.

Remark: Channel switching is done after bus initialization completed.

After connection is requested and Bus Initialization requested (BUSINIT = 1),

an interrupt on INT will not be generated when the bus initialization is done

(masked).

Remark: Channel switching is done after bus initialization completed.

INTINMSK

R/W

Interrupt on INT_IN will generate an interrupt on INT.

Interrupt on INT_IN will not generate an interrupt on INT (masked)

Table 6.

Legend: * default value

Bit

Symbol

Access Value[1] Description

Table 7.

NTESTON

TESTON

BUSINIT

NBUSON

BUSON

NMYBUS

MYBUS

Table 8.

Legend: * default value

Bit

Symbol

Access Value[1]

Description

NTESTON

R/W

A logic level HIGH to the INT line of the other channel is sent (interrupt

cleared).

A logic level LOW to the INT line of the other channel is sent (interrupt

generated).

TESTON

R/W

A logic level HIGH to the INT line is sent (interrupt cleared).

A logic level LOW to the INT line is sent (interrupt generated).

R only

not used

BUSINIT

R/W

Bus initialization is not requested.

Bus initialization is requested.

NBUSON

R only

see

Table 11

NBUSON bit along with BUSON bit decides whether any upstream channel

is connected to the downstream channel or not. See Table 10, Table 11, and

Table 12.

BUSON

R/W

see

Table 11

BUSON bit along with the NBUSON bit decides whether any upstream

channel is connected to the downstream channel or not. See Table 10,

Table 11, and Table 12.

NMYBUS

R only

see

Table 11

NMYBUS bit along with MYBUS bit decides which upstream channel is

connected to the downstream channel. See Table 9, Table 11, and Table 12.

MYBUS

R/W

see

Table 11

MYBUS bit along with the NMYBUS bit decides which upstream channel is

connected to the downstream channel. See Table 9, Table 11, and Table 12.

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