PCA9541APWSLASH03 datasheet(8/41 Pages) NXP

8 / 41 page

PCA9541A_3

Product data sheet

Rev. 03 — 16 July 2009

8 of 41

NXP Semiconductors

PCA9541A

2-to-1 I2C-bus master selector with interrupt logic and reset

• During a write operation, the PCA9541A will acknowledge bytes sent to the IE and

CONTROL registers, but will not acknowledge a byte sent to the Interrupt Status

over to 00b but stay at 10b.

Only the 2 least signiﬁcant bits are affected by the AI ﬂag.

Unused bits must be programmed with zeros. Any command code (write operation)

different from ‘000AI 0000’, ‘000AI 0001’, and ‘000AI 0010’ will not be acknowledged. At

power-up, this register defaults to all zeros.

Each system master controls its own set of registers, however they can also read speciﬁc

bits from the other system master.

8.3 Interrupt Enable and Control registers description

When a master seeks control of the bus by connecting its I2C-bus channel to the

PCA9541A downstream channel, it has to write to the CONTROL register (Reg#01).

Bits MYBUS and BUSON allow the master to take control of the bus.

The MYBUS and the NMYBUS bits determine which master has control of the bus.

Table 9 explains which master gets control of the bus and how. There is no arbitration. Any

master can take control of the bus when it wants regardless of whether the other master is

using it or not.

The BUSON and the NBUSON bits determine whether the upstream bus is connected or

disconnected to/from the downstream bus. Table 10 explains when the upstream bus is

connected or disconnected.

Internally, the state machine does the following:

• If the combination of the BUSON and the NBUSON bits causes the upstream to be

disconnected from the downstream bus, then that is done. So in this case, the values

of the MYBUS and the NMYBUS do not matter.

Table 4.

Command Code register

Type

R/W

interrupt enable

CONTROL

R/W

control switch

ISTAT

R only

interrupt status

not allowed

Fig 7.

Internal register map

002aae660

IE 0

CONTROL 0

ISTAT 0

IE 1

CONTROL 1

ISTAT 1

PCA9541A

REG#00

REG#01

REG#10

CONTROL

ISTAT

MASTER 0

SCL_MST0

SDA_MST0

REG#00

REG#01

REG#10

CONTROL

ISTAT

MASTER 1

SCL_MST1

SDA_MST1

PCA9541APW/03 датащи(PDF) 8 Page - NXP Semiconductors

PCA9541APW/03 датащи(HTML) 8 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

датащи скачать

ссылки URL