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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PCA9541AD/03 датащи(PDF) 30 Page - NXP Semiconductors |
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PCA9541AD/03 датащи(HTML) 30 Page - NXP Semiconductors |
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30 / 41 page  PCA9541A_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 16 July 2009 30 of 41 NXP Semiconductors PCA9541A 2-to-1 I2C-bus master selector with interrupt logic and reset 13. Dynamic characteristics [1] Pass gate propagation delay is calculated from the 20 Ω typical Ron and the 15 pF load capacitance. [2] After this period, the first clock pulse is generated. [3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. Table 17. Dynamic characteristics Symbol Parameter Conditions Standard-mode I2C-bus Fast-mode I2C-bus Unit Min Max Min Max tPD propagation delay (SDA_MSTn to SDA_SLAVE) or (SCL_MSTn to SCL_SLAVE) [1] - 0.3 - 0.3 ns fSCL SCL clock frequency 0 100 0 400 kHz fSCL(init/rec) SCL clock frequency (bus initialization/bus recovery) 50 150 50 150 kHz tBUF bus free time between a STOP and START condition 4.7 - 1.3 - µs tHD;STA hold time (repeated) START condition [2] 4.0 - 0.6 - µs tLOW LOW period of the SCL clock 4.7 - 1.3 - µs tHIGH HIGH period of the SCL clock 4.0 - 0.6 - µs tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - µs tSU;STO set-up time for STOP condition 4.0 - 0.6 - µs tHD;DAT data hold time 0[3] 3.45 0[3] 0.9 µs tSU;DAT data set-up time 250 - 100 - ns tr rise time of both SDA and SCL signals - 1000 20 + 0.1Cb[4] 300 ns tf fall time of both SDA and SCL signals - 300 20 + 0.1Cb[4] 300 ns Cb capacitive load for each bus line - 400 - 400 pF tSP pulse width of spikes that must be suppressed by the input filter - 50 - 50 ns tVD;DAT data valid time HIGH-to-LOW [5] -1 - 1 µs LOW-to-HIGH [5] - 0.6 - 0.6 µs tVD;ACK data valid acknowledge time - 1 - 1 µs INT tv(INT_IN-INTn) valid time from pin INT_IN to pin INTn signal -4 - 4 µs td(INT_IN-INTn) delay time from pin INT_IN to pin INTn inactive -2 - 2 µs tw(rej)L LOW-level rejection time INT_IN input 1 - 1 - µs tw(rej)H HIGH-level rejection time INT_IN input 0.5 - 0.5 - µs RESET tw(rst)L LOW-level reset time 10 - 10 - ns trst reset time SDA clear 500 - 500 - ns tREC;STA recovery time to START condition [6][7] 0- 0 - ns |
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