PCA9541ADSLASH03 datasheet(16/41 Pages) NXP

16 / 41 page

PCA9541A_3

Product data sheet

Rev. 03 — 16 July 2009

16 of 41

NXP Semiconductors

PCA9541A

2-to-1 I2C-bus master selector with interrupt logic and reset

8.4.3 Downstream interrupt

An interrupt can also be generated by a downstream device by asserting the INT_IN pin

LOW. When INT_IN is asserted LOW and if both INTINMSK bits are not set to ‘1’ by either

master, INT0 and INT1 both go LOW.

By setting the INTINMSK bit to ‘1’ by a master and/or the INTINMSK bit to ‘1’ by the other

master, the interrupt(s) is (are) masked and the corresponding masked channel(s) does

(do) not receive an interrupt (INT0 and/or INT1 line does (do) not go LOW).

8.4.4 Functional test interrupt

A master can send an interrupt to itself to test its own INT wire or send an interrupt to the

other master to test its INT line. This is done by:

• setting the TESTON bit to ‘1’ to test its own INT line

• setting the NTESTON bit to ‘1’ to test the other master INT line

Setting the TESTON and/or NTESTON bits to ‘0’ by a master will clear the interrupt(s).

Remark: Interrupt outputs have an open-drain structure. Interrupt input does not have any

internal pull-up resistor and must not be left ﬂoating (that is, pulled HIGH to VDD through

resistor) in order to avoid any undesired interrupt conditions.

8.4.5 Register 2: Interrupt Status Register (B1:B0 = 10b)

The Interrupt Status Register for both the masters is identical and is described below.

Nevertheless, there are physically 2 internal Interrupt Registers, one for each upstream

channel.

When Master 0 reads this register, the internal Interrupt Register 0 will be accessed.

When Master 1 reads this register, the internal Interrupt Register 1 will be accessed.

Table 13.

NMYTEST

MYTEST

BUSLOST

BUSOK

BUSINIT

INTIN

Table 14.

Legend: * default value

Bit

Symbol

Access Value[1] Description

NMYTEST[2]

R only

no interrupt generated due to NTESTON bit from the other master

(NTESTON = 0 from the other master)[3]

interrupt generated due to TESTON bit from the other master

(NTESTON = 1 from the other master)[3]

MYTEST[2]

R only

no interrupt generated by TESTON bit (TESTON = 0)[3]

interrupt generated by TESTON bit (TESTON = 1)[3]

R only

not used

R only

not used

BUSLOST[4]

R only

no interrupt generated to the previous master when switching to the new one

is initiated

interrupt generated to the previous master when switching to the new one is

initiated

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