PCA9541ADSLASH03 datasheet(2/41 Pages) NXP

2 / 41 page

PCA9541A_3

Product data sheet

Rev. 03 — 16 July 2009

2 of 41

NXP Semiconductors

PCA9541A

2-to-1 I2C-bus master selector with interrupt logic and reset

An active LOW reset input allows the PCA9541A to be initialized. Pulling the RESET pin

LOW resets the I2C-bus state machine and conﬁgures the device to its default state as

does the internal Power-On Reset (POR) function.

Features

I 2-to-1 bidirectional master selector

I I2C-bus interface logic; compatible with SMBus standards

I PCA9541A/01 powers up with Channel 0 selected

I PCA9541A/03 powers up with no channel selected and either master can take control

of the bus

I Active LOW interrupt input

I 2 active LOW interrupt outputs

I Active LOW reset input

I 4 address pins allowing up to 16 devices on the I2C-bus

I Channel selection via I2C-bus

I Bus initialization/recovery function

I Bus trafﬁc sensor

I Low Ron switches

I Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses

I No glitch on power-up

I Supports hot insertion

I Software identical for both masters

I Low standby current

I Operating power supply voltage range of 2.3 V to 5.5 V

I 6.0 V tolerant inputs

I 0 Hz to 400 kHz clock frequency

I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

I Packages offered: SO16, TSSOP16, HVQFN16

Applications

I High reliability systems with dual masters

I Gatekeeper multiplexer on long single bus

I Bus initialization/recovery for slave devices without hardware reset

I Allows masters without arbitration logic to share resources

PCA9541AD/03 датащи(PDF) 2 Page - NXP Semiconductors