X

8

Q

© 2010 Exar Corporation

19/27

Rev. 1.0.3

within +/- 5% of the external clock frequency. A higher Main Oscillator frequency will not improve

accuracy or any performance efficiency.

There are several considerations when choosing the PWM switching frequency.

Minimum On Time

Minimum on time determines the minimum duty cycle at the specific switching frequency. The

minimum on time for the XRP7708 is 40ns.

%

100

As an example the minimum duty cycle is 4% for 1MHz PWM frequency. This is important since the

minimum on time dictates the maximum conversion ratio that the PWM controller can achieve.

%

Maximum Duty Cycle

The maximum duty cycle is dictated by the minimum required time to sample the current when the

low side MOSFET is on. For the XRP7708, the minimum required sampling time is about 16 clock

cycles at the main oscillator frequency. When calculating maximum duty cycle, the sampling time

needs to be subtracted using the below equation. For example, if operating at 1MHz using the

32MHz main oscillator frequency, the maximum duty cycle would be:

%

1

16

0.03

100

47%

On the other hand, if the 48MHz main oscillator frequency was chosen for the 1MHz PWM

frequency, the maximum duty cycle would be:

%

1

16

0.03

100

64%

Therefore, it is best to choose the highest main oscillator frequency for a particular PWM frequency

if duty cycle limit might be encountered. The maximum duty cycle for any PWM frequency can

easily be determined using the following table:

Main Oscillator Frequency

Maximum Duty Cycle

48MHz

44.8MHz 41.6MHz 38.4MHz 35.2MHz

32MHz

28.8Mhz 25.6MHz

47%

1.5MHz

1.4MHz

1.3MHz

1.2MHz

1.1MHz

1.0MHz

900KHz

800KHz

64%

1.0MHz

933KHz

867KHz

800KHz

733KHz

667KHz

600KHz

533KHz

72%

750KHz

700KHz

650KHz

600KHz

550KHz

500KHz

450KHz

400KHz

77%

600KHZ

560KHz

520KHz

480KHz

440KHz

400KHz

360KHz

320KHz

80%

500KHz

467KHZ

433KHz

400KHz

367KHz

333KHz

300KHz

NA

83%

429KHZ

400KHZ

370KHz

343KHz

314KHz

NA

NA

NA

85%

375KHz

350KHz

325KHz

300KHz

NA

NA

NA

NA

Fig. 21: PWM Frequency

It is highly recommended that the maximum duty cycle obtained from the table above be

programmed into each of the channels using the SET_DUTY_LIMITER_CHx register. This ensures

that under all conditions (including faults), there will always be sufficient sampling time to measure

the output current. When the duty cycle limit is reached, the output voltage will no longer regulate

and will be clamped based on the maximum duty cycle limit setting.

Efficiency