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8

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© 2010 Exar Corporation

17/27

Rev. 1.0.3

The XRP7708 also offers an Over-Current warning flag. This warning flag resides in the

READ_OVC_FLAG register. The warning flag bit will be set when the output current gets to within a

specified value of the output current limit threshold enabling the host to reduce power

consumption. The SET_VIOUT_MAX_CHx register allows the warning flag threshold to be set 10mV,

20mV, 30mV or 40mV below VIOUT_MAX. The warning flag will be automatically cleared when the

current drops below the warning threshold.

Over-Current Fault Handling

When an over-current condition occurs, PWM drivers in the corresponding channels are disabled.

After a 200ms timeout, the controller is re-powered and soft-start is initiated. When the over-

current condition is reached the controller will check the SET_FAULT_RESP_CONFIG_LB and

SET_FAULT_RESP_CONFIG_HB to determine whether there are any “following” channels that need

to be similarly restarted. The controller will also set the fault flags in READ_OVC_FAULT_WARN

register.

Typically the over-current fault threshold would be set to 130-140% of the maximum desirable

output current. This will help avoid any over-current conditions caused by transients that would

shut down the output channel.

CHIP OPERATION AND CONFIGURATION

The SET_SS_RISE_CHx register is a 16 bit register which specifies the soft-start delay and the

ramp characteristics for a specific channel. This register allows the customer to program the

channel with a 250us step resolution and up to a maximum 16ms delay.

Bits [15:10] specify the delay after enabling a channel but before outputting pulses; where each bit

represents 250us steps. Bits [9:0] specify the rise time of the channel; these 10 bits define the

number of microseconds for each 50mV increment to reach the target voltage.

Fig. 19: Channel POwer Up Sequence

The SET_PD_FALL_CHx register is a 16 bit register. This register specifies the soft-stop delay and

ramp (fall-time) characteristics for when the chip receives a channel disable indication from the

Host to shutdown the channel.

Bits [15:10] specify the delay after disabling a channel but before starting the shutdown of the

channel; where each bit represents 250us steps. Bits [9:0] specify the fall time of the channel;

these 10 bits define the number of microseconds for each 50mV increment to reach the discharge

threshold.

 

Enable

Signal

Vout

SS_RISE_CHx

REGISTER

Bit [9:0]

RISE TIME

DELAY

Bit [15:10]