X

8

Q

© 2010 Exar Corporation

18/27

Rev. 1.0.3

Fig. 20: Channel Soft-Stop Sequence

The XRP7708 allows the user to set the upper and lower bound for a power good signal per

channel.

The

SET_PWRG_TARG_MAX_CHx

register

sets

the

upper

bound,

the

SET_PWRG_TARG_MIN_CHx register sets the lower bound. Each register has a 20mV LSB

resolution. When the output voltage is within bounds the power good signal is asserted high.

Typically the upper bound should be lower than the over-voltage threshold. In addition, the power

good signal can be delayed by a programmable amount set in the SET_PWRGD_DLY_CHx register.

The power good delay is only set after the soft-start period is finished. If the channel has a pre-

charged condition that falls into the power good region, a power good flag is not set until the soft-

start is finished.

The PWM switching frequency is set by choosing the corresponding oscillator frequency and clock

divider ratio in the SET_SW_FREQUENCY register. Bits [6:4] set the oscillator frequency and bits

[2:0] set the clock divider. The tables below summarize the available Main Oscillator and PWM

switching frequency settings in the XRP7708.

Main Oscillator Frequency

SET_SW_FREQUENCY[6:4]

000

001

010

011

100

101

110

111

Main Oscillator Frequency

48MHz

44.8MHz 41.6MHz 38.4MHz 35.2MHz

32MHz

28.8Mhz 25.6MHz

Ts

20.8ns

22.3ns

24ns

26ns

28.4ns

31.25ns

34.7ns

39ns

PWM Switching Frequency

SET_SW_FREQUENCY[6:4]

SET_SW_FREQUENCY[2:0]

000

001

010

011

100

101

110

111

000

NA

NA

NA

NA

NA

NA

NA

NA

001

1.5MHz

1.4MHz

1.3MHz

1.2MHz

1.1MHz

1.0MHz

900KHz

800KHz

010

1.0MHz

933KHz

867KHz

800KHz

733KHz

667KHz

600KHz

533KHz

011

750KHz

700KHz

650KHz

600KHz

550KHz

500KHz

450KHz

400KHz

100

600KHZ

560KHz

520KHz

480KHz

440KHz

400KHz

360KHz

320KHz

101

500KHz

467KHZ

433KHz

400KHz

367KHz

333KHz

300KHz

NA

110

429KHZ

400KHZ

370KHz

343KHz

314KHz

NA

NA

NA

111

375KHz

350KHz

325KHz

300KHz

NA

NA

NA

NA

There are a number of options that could result in similar PWM switching frequency as shown

above. In general, the chip consumes less power at lower oscillator frequency. When

synchronization to external clock is needed, the user can choose the oscillator frequency to be

 

DELAY

FALL TIME

Bit [15:10]

Bit [9:0]

Vout

Enable

Signal

PD_DELAY_CHx

REGISTER