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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LPC2921 датащи(PDF) 52 Page - NXP Semiconductors |
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LPC2921 датащи(HTML) 52 Page - NXP Semiconductors |
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52 / 84 page  LPC2921_23_25_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 14 April 2010 52 of 84 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN, LIN, and USB Interrupt-request masking is performed individually per interrupt target by comparing the priority level assigned to a specific interrupt request with a target-specific priority threshold. The priority levels are defined as follows: • Priority level 0 corresponds to ‘masked’ (i.e. interrupt requests with priority 0 never lead to an interrupt). • Priority 1 corresponds to the lowest priority. • Priority 15 corresponds to the highest priority. Software interrupt support is provided and can be supplied for: • Testing RTOS (Real-Time Operating System) interrupt handling without using device-specific interrupt service routines. • Software emulation of an interrupt-requesting device, including interrupts. 6.16.2 Clock description The VIC is clocked by CLK_SYS_VIC, see Section 6.7.2. |
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