LPC2921 datasheet(47/84 Pages) NXP

47 / 84 page

LPC2921_23_25_3

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Product data sheet

Rev. 03 — 14 April 2010

47 of 84

NXP Semiconductors

LPC2921/2923/2925

ARM9 microcontroller with CAN, LIN, and USB

6.15.3 Clock generation for USB (CGU1)

The CGU1 block is functionally identical to the CGU0 block and generates the clock for

the USB interface and a dedicated output clock. The CGU1 block uses its own PLL and

fractional divider. The PLLs used in CGU0 and CGU1 are identical (see Section 6.15.2.2).

The clock input to the CGU1 PLL is provided by one of two base clocks generated in the

CGU0: BASE_ICLK0_CLK or BASE_ICLK1_CLK. The base clock not used for the PLL

can be configured to drive the output clock directly.

6.15.3.1

Pin description

The CGU1 module in the LPC2921/2923/2925 has the pins listed in Table 25 below.

6.15.4 Reset Generation Unit (RGU)

The RGU controls all internal resets.

The key features of the Reset Generation Unit (RGU) are:

• Reset controlled individually per subsystem

• Automatic reset stretching and release

• Monitor function to trace resets back to source

Fig 12. Block diagram of the CGU1

PLL

FDIV0

OUT 0

OUT 2

002aae250

clkout

clkout120

clkout240

CLOCK GENERATION UNIT

(CGU1)

AHB TO DTL BRIDGE

BASE_USB_CLK

BASE_OUT_CLK

BASE_ICLK1_CLK

BASE_ICLK0_CLK

Table 26.

CGU1 pins

Symbol

Direction

Description

CLK_OUT

OUT

clock output

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