CS8415A-CSZ datasheet(18/46 Pages) CIRRUS

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DS470F4

CS8415A

6. CONTROL PORT DESCRIPTION AND TIMING

The control port is used to access the registers, allowing the CS8415A to be configured for the desired operational

modes and formats. In addition, Channel Status and User data may be read through the control port. The operation

of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid

potential interference problems, the control port pins should remain static if no operation is required.

The control port has 2 modes: SPI and I²C, with the CS8415A acting as a slave device. SPI mode is selected if

there is a high-to-low transition on the AD0/CS pin, after the RST pin has been brought high. I²C mode is selected

by connecting the AD0/CS pin to VL+ or DGND, thereby permanently selecting the desired AD0 bit address state.

6.1

SPITM Mode

In SPI mode, CS is the CS8415A chip select signal, CCLK is the control port bit clock (input into the

CS8415A from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the out-

put data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.

Figure 8 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first

seven bits on CDIN form the chip address and must be 0010000b. The eighth bit is a read/write indicator

(R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is

set to the address of the register that is to be updated. The next eight bits are the data which will be placed

into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be

externally pulled high or low with a 47 k

Ω resistor, if desired.

There is a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero,

the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will autoincrement

after each byte is read or written, allowing block reads or writes of successive registers.

To read a register, the MAP has to be set to the correct address by executing a partial write cycle which

finishes (CS high) immediately after the MAP byte. The MAP auto increment bit (INCR) may be set or not,

as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high.

The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high

impedance state). If the MAP auto increment bit is set to 1, the data for successive registers will appear

consecutively.

MA P

MSB

LSB

DATA

byte 1

by te n

R/W

AD D R ES S

CH IP

ADDRESS

CH IP

CD IN

CC L K

CD O U T

MSB

LSB MSB

LSB

0010000

MAP = Memory Address Pointer, 8 bits, MSB first

High Impedance

Figure 8. Control Port Timing in SPI Mode

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