SS8017 datasheet(15/16 Pages) SSC

15 / 16 page

though reads and writes at VCC levels below 3V are not

recommended. A second Vcc comparator, the ADC

UVLO comparator, prevents the ADC from converting

until there is sufficient headroom (Vcc = 2.8V typical).

Power-Up Defaults:

n Interrupt latch is cleared.

n ADC begins auto /converting at a 0.25Hz rate.

n Command byte is set to 00h to facilitate quick re-

mote Receive Byte queries.

n THIGH and TLOW registers are set to max and min

limits, respectively

Thermal Shutdown Signal

When the temperature of DX1 reaches or exceeds the

Tcrit1 threshold consecutively for the times equal to

the number of faults of the FQ_TH_SHUT registers,

TH_SHUT pin becomes logic high. The same mecha-

nism is duplicated for DX2. There fore, either one of

DX1, DX2 continuously over their respective Tcrit, the

TH_SHUT will assert logic high to indicate a thermal

shutdown event.

Figure 6. SMBus Write Timing Diagram

A = start condition

H = LSB of data clocked into slave

B = MSB of address clocked into slave

I = slave pulls SMBDATA line low

C = LSB of address clocked into slave

J = acknowledge clocked into master

D = R / W bit clocked into slave

K = acknowledge clocked pulse

E = slave pulls SMB Data line low

L = stop condition data executed by slave

F = acknowledge bit clocked into master

M = new start condition

G = MSB of data clocked into slave

Figure 7. SMBus Read Timing Diagram

A = start condition

G = MSB of data clocked into master

B = MSB of address clocked into slave

H = LSB of data clocked into master

C = LSB of address clocked into slave

I = acknowledge clocked pulse

D = R / W bit clocked into slave

J = stop condition

E = slave pulls SMBDATA line low

K= new start condition

F =acknowledge bit clocked into master

SMBCLK

SMBDATA

E F

SU:STA

HD:STA

SU :DAT

HD:DAT

SU:STO

BUF

LOW

HIGH

SMBCLK

SMBDATA

E F

SU:STA

HD :STA

SU:DAT

SU:STO

BUF

LOW

HIGH

SMBCLK

SMBDATA

E F

SU:STA

HD :STA

SU:DAT

SU:STO

BUF

LOW

HIGH

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SS8017

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