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WM8731 датащи(PDF) 38 Page - Wolfson Microelectronics plc

номер детали WM8731
подробное описание детали  Portable Internet Audion CODEC with Headphone Driver and Programmable Sample Rates
PDF  56 Pages
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производитель  WOLFSON [Wolfson Microelectronics plc]
домашняя страница  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8731 датащи(HTML) 38 Page - Wolfson Microelectronics plc

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WM8731
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 2.0 February 2001
38
SAMPLING
RATE
ADC
DAC
MCLK
FREQUENCY
SAMPLE
RATE
REGISTER SETTINGS
DIGITAL
FILTER
TYPE
kHz
kHz
MHz
BOSR
SR3
SR2
SR1
SR0
12.288
0
0
0
0
0
48
48
18.432
1
0
0
0
0
1
12.288
0
0
0
0
1
48
8
18.432
1
0
0
0
1
1
12.288
0
0
0
1
0
848
18.432
1
0
0
1
0
1
12.288
0
0
0
1
1
88
18.432
1
0
0
1
1
1
12.288
0
0
1
1
0
32
32
18.432
1
0
1
1
0
1
12.288
0
0
1
1
1
96
96
18.432
1
0
1
1
1
2
11.2896
0
1
0
0
0
44.1
44.1
16.9344
1
1
0
0
0
1
11.2896
0
1
0
0
1
44.1
8
(Note 1)
16.9344
1
1
0
0
1
1
11.2896
0
1
0
1
0
8
(Note 1)
44.1
16.9344
1
1
0
1
0
1
11.2896
0
1
0
1
1
8
(Note 1)
8
(Note 1)
16.9344
1
1
0
1
1
1
11.2896
0
1
1
1
1
88.2
88.2
16.9344
1
1
1
1
1
2
Table 17 Normal Mode Sample Rate Look-up Table
Notes:
1.
8k not exact, actual = 8.018kHz
2.
All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid
The BOSR bit represents the base over-sampling rate. This is the rate that the WM8731 digital signal
processing is carried out at. In Normal mode, with BOSR = 0, the base over-sampling rate is at
256fs, with BOSR = 1, the base over-sampling rate is at 384fs. This can be used to determine the
actual audio data rate produced by the ADC and required by the DAC.
Example scenarios are:
1.
with a requirement that the ADC data rate is 8kHz and DAC data rate is 48kHz, then choosing
MCLK = 12.288MHz the device is programmed with BOSR = 0 (256fs), SR3 = 0, SR2 = 0, SR1
= 1, SR0 = 0.The ADC output data rate will then be exactly 8kHz (derived from 12.288MHz/256
x1/6) and the DAC expects data at exactly 48kHz (derived from 12.288MHz/256)
2.
with a requirement that ADC data rate is 8kHz and DAC data rate is 44.1kHz, then choosing
MCLK = 16.9344MHz the device is programmed with BOSR = 1 (384fs), SR3 = 1, SR2 = 0, SR1
= 0, SR0 = 1. The ADC will no longer output data at exactly 8.000kHz, instead it will be
8.018kHz (derived from 16.9344MHz/384 x 2/11), the DAC still is at exactly 44.1kHz (derived
from 16.9344MHz/384). A slight (sub 0.5%) pitch shift will therefore result in the 8kHz audio
data and (importantly) the user must ensure that the data across the digital interface is correctly
synchronised at the 8.018kHz rate.



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