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WM8731 датащи(PDF) 33 Page - Wolfson Microelectronics plc |
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WM8731 датащи(HTML) 33 Page - Wolfson Microelectronics plc |
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33 / 56 page ![]() WM8731 Advanced Information WOLFSON MICROELECTRONICS LTD AI Rev 2.0 February 2001 33 LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC BCLK DACDAT/ ADCDAT 1/fs n 3 2 1 n-2 n-1 LSB MSB n 3 2 1 n-2 n-1 LSB MSB 1 BCLK 1 BCLK Figure 26 I2S Mode Right Justified mode is where the LSB is available on the rising edge of BCLK preceding a LRCLK transition, yet MSB is still transmitted first. LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC BCLK DACDAT/ ADCDAT 1/fs n 3 2 1 n-2 n-1 LSB MSB n 3 2 1 n-2 n-1 LSB MSB Figure 27 Right Justified Mode DSP mode is where the left channel MSB is available on either the 1 st or 2nd rising edge of BCLK (selectable by LRP) following a LRC transition high. Right channel data immediately follows left channel data. LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC BCLK DACDAT/ ADCDAT n 3 2 1 n-2 n-1 LSB MSB n 3 2 1 n-2 n-1 1 BCLK Input Word Length (IWL) Note: Input word length is defined by the IWL register, LRP = 1 1/fs Figure 28 DSP Mode |
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