NX2139A datasheet(16/21 Pages) MICROSEMI

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NX2139A

Rev. 2.3

03/19/09

Here C

C is chosen to be 33pF. For electrolytic or

POSCAP, R

C is typically

selected to be zero.

f2 is determined by the desired output voltage.

REF

LDOOUT

REF

7.5k

0.75V

1.5V

0.75V

=7.5k

−

Ω×

−

Ω

Choose R

f2=7.5kΩ.

When ceramic capacitors or some low ESR bulk

capacitors are chosen as LDO output capacitors, the

zero caused by output capacitor ESR is so high that

crossover frequency F

O has to be chosen much higher

than zero caused by R

C and CC and much lower than

zero caused by ESR . For example, 10uF ceramic is

used as output capacitor. We select Fo=300kHz,

f1=7.5kohm and select

MOSFET SI4800(g

m=19). RC

and C

C can be calculated as follows.

OUT

1+g

R =R

1.5V

1+19S

300kHz 20uF

=7.5k

1.5V

19S

=14.9k

×π ××

××

×π ××

Ω ××

Ω

Typically R

C is chosen to be 1 to 1.5 times smaller

than calculated value to compensate parasitic effect.

Choose R

C=20kΩ.

10C

10 20uF

20k

19S

=0.53nF

Ω×

Choose C

C=1000pF.

Current Limit for LDO

Current limit of LDO is achieved by sensing the

LDO feedback voltage. When LDO_FB pin is below

70% of V

REF, the IC goes into latch mode.

The IC will

turn off all the channel until VCC or ENSW resets.

Power Good for LDO

Power good output is open drain output, a pull

up resistor is needed. Typically when softstart is

finised and LDOFB pin voltage is over 90% of V

REF,

the LDOPGOOD pin is pulled to high.

Layout Considerations

The layout is very important when designing high

frequency switching converters. Layout will affect noise

pickup and can cause a good design to perform with

less than expected results.

There are two sets of components considered in

the layout which are power components and small sig-

nal components. Power components usually consist of

input capacitors, high-side MOSFET, low-side

MOSFET, inductor and output capacitors. A noisy en-

vironment is generated by the power components due

to the switching power. Small signal components are

connected to sensitive pins or nodes. A multilayer lay-

out which includes power plane, ground plane and sig-

nal plane is recommended .

Layout guidelines:

1. First put all the power components in the top

layer connected by wide, copper filled areas. The input

capacitor, inductor, output capacitor and the MOSFETs

should be close to each other as possible. This helps

to reduce the EMI radiated by the power loop due to

the high switching currents through them.

2. Low ESR capacitor which can handle input

RMS ripple current and a high frequency decoupling

ceramic cap which usually is 1uF

need to be practi-

cally touching the drain pin of the upper MOSFET, a

plane connection is a must.

3. The output capacitors should be placed as close

as to the load as possible and plane connection is re-

quired.

4. Drain of the low-side MOSFET and source of

the high-side MOSFET need to be connected thru a

plane and as close as possible. A snubber needs to be

placed as close to this junction as possible.

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