PixArt Imaging Inc.

PAC107

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38

PixArt Imaging Inc.

E-mail:

fae_service@pixart.com.tw

V1.4, Aug, 2005

At S6P2 of the following cycle, hardware shifts the LSB (D0) onto the RXD pin. At S3P1

of the next cycle, the TXD pin goes low for the first clock-signal pulse. Shifts continue

every peripheral cycle. In the 9

RXD pin. At the beginning of the tenth cycle, hardware drives the RXD pin high and assert

TI (S1P1) to indicate an end of transmission.

Reception (Mode 0)

To start a reception in mode 0, write to the SCON register. Clear SM0, SM1, and RI and set

REN. Hardware executes the write to SCON in the last phase (S6P2) of a peripheral cycle.

Write to SCON in the second peripheral cycle, TXD goes low at S3P1 for the first clock,

and the LSB (D0) is sampled on RXD pin at S5P2. D0 bit is then shifted into the shift

TXD

Write to

SBUF

Shift

RXD

TI

TXD

Write to

SBUF

Shift

RXD

RI

S3P1

S6P1

S6P2

S6P2

S6P2

S6P2

S6P2

S6P2

S6P2

S1P1

D0

D1

D2

D6

D7

S3P1

S6P1

S6P2

S6P2

S6P2

S6P2

S6P2

S6P2

S6P2

S5P2

S1P1

D0

D1

D6

D0

D7

Transmit

Receive

Mode 0 Timing

Set REN, Clear RI