PixArt Imaging Inc.

PAC107

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

26

PixArt Imaging Inc.

V1.4, Aug, 2005

4. ON-CHIP PERIPHERALS

4.1 Interrupts

Interrupt Source

Request Flag

Priority Flag

Enable Flag

Vector

Address

Priority-

Within-Level

Flog Cleared by

Hardware?

External Request

IE0/TCON.1

PX0/IP.0

EX0/IE.0

0003h

1

Edge-Yes

Level-No

Internal Timer0/Counter0

TF0/TCON.5

PT0/IP.1

ET0/IE.1

000Bh

2

Yes

External Request

IE1/TCON.3

PX1/IP.2

EX1/IE.2

0013h

3

Edge-Yes

Level-No

Internal Timer1/Counter1

TF1/TCON.7

PT1/IP.3

ET1/IE.3

001Bh

4

Yes

Xmit

Ti/SCON.1

Internal Serial Port

Rcvr

RI/SCON.0

PS/IP.4

ES/IE.4

0023h

5

No

TF2/T2CON.7

Internal Timer2/Counter2

EXF2/TSCON.6

PT2/IP.5

ET2/IE.5

002Bh

6

No

Interrupt System Table

External Interrupt

External Interrupt

0

INT

is modified as a Sensor control pin. The

1

INT

pins can be

0

1

TF0

0

1

IE0

Timer 0

EA

EX0

ET0

EX1

Interrupt Enable

IP

Priority Enable

Highest

Priority

Interrupt

Interrupt Control System Configuration

INT1

INT0

IT0

IT1

PFI

Power Fail Detector

IE1

Timer 1

TF1

ET1

RI

TI

Receive

Transmit

ES

ET2

EXF2

TF2

Timer 2

T2EX

EPFI

PX0

PT0

PX1

PT1

PS

PT2