PIC12F615 datasheet(20/212 Pages) MICROCHIP

20 / 212 page

PIC12F609/615/617/12HV609/615

DS41302D-page 20

 2010 Microchip Technology Inc.

2.2.2.3

INTCON Register

The INTCON register is a readable and writable

for TMR0 register overflow, GPIO change and external

GP2/INT pin interrupts.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE of the INTCON register.

User

software

should

ensure

the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

INTCON: INTERRUPT CONTROL REGISTER

R/W-0

GIE

PEIE

T0IE

INTE

GPIE

T0IF

INTF

GPIF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

GIE: Global Interrupt Enable bit

= Enables all unmasked interrupts

= Disables all interrupts

bit 6

PEIE: Peripheral Interrupt Enable bit

= Enables all unmasked peripheral interrupts

= Disables all peripheral interrupts

bit 5

T0IE: Timer0 Overflow Interrupt Enable bit

= Enables the Timer0 interrupt

= Disables the Timer0 interrupt

bit 4

INTE: GP2/INT External Interrupt Enable bit

= Enables the GP2/INT external interrupt

= Disables the GP2/INT external interrupt

bit 3

GPIE: GPIO Change Interrupt Enable bit(1)

= Enables the GPIO change interrupt

= Disables the GPIO change interrupt

bit 2

T0IF: Timer0 Overflow Interrupt Flag bit(2)

= Timer0 register has overflowed (must be cleared in software)

= Timer0 register did not overflow

bit 1

INTF: GP2/INT External Interrupt Flag bit

= The GP2/INT external interrupt occurred (must be cleared in software)

= The GP2/INT external interrupt did not occur

bit 0

GPIF: GPIO Change Interrupt Flag bit

= When at least one of the GPIO <5:0> pins changed state (must be cleared in software)

= None of the GPIO <5:0> pins have changed state

Note 1:

IOC register must also be enabled.

T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before

clearing T0IF bit.

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