PIC12F615 datasheet(70/212 Pages) MICROCHIP

70 / 212 page

PIC12F609/615/617/12HV609/615

DS41302D-page 70

 2010 Microchip Technology Inc.

9.5

Comparator Interrupt Operation

The comparator interrupt flag can be set whenever

there is a change in the output value of the comparator.

Changes are recognized by means of a mismatch

circuit which consists of two latches and an exclusive-

or gate (see Figure 9-4 and Figure 9-5). One latch is

updated with the comparator output level when the

CMCON0 register is read. This latch retains the value

until the next read of the CMCON0 register or the

occurrence of a Reset. The other latch of the mismatch

circuit is updated on every Q1 system clock. A

mismatch condition will occur when a comparator

output change is clocked through the second latch on

the Q1 clock cycle. At this point the two mismatch

latches have opposite output levels which is detected

by the exclusive-or gate and fed to the interrupt

circuitry. The mismatch condition persists until either

the CMCON0 register is read or the comparator output

returns to the previous state.

The comparator interrupt is set by the mismatch edge

and not the mismatch level. This means that the

interrupt flag can be reset without the additional step of

reading or writing the CMCON0 register to clear the

mismatch registers. When the mismatch registers are

cleared, an interrupt will occur upon the comparator’s

return to the previous state, otherwise no interrupt will

be generated.

Software will need to maintain information about the

status of the comparator output, as read from the

CMCON1 register, to determine the actual change that

has occurred.

The CMIF bit of the PIR1 register is the Comparator

Interrupt flag. This bit must be reset in software by

clearing it to ‘0’. Since it is also possible to write a '1' to

this register, an interrupt can be generated.

The CMIE bit of the PIE1 register and the PEIE and GIE

bits of the INTCON register must all be set to enable

comparator interrupts. If any of these bits are cleared,

the interrupt is not enabled, although the CMIF bit of

the PIR1 register will still be set if an interrupt condition

occurs.

FIGURE 9-4:

COMPARATOR

INTERRUPT TIMING W/O

CMCON0 READ

FIGURE 9-5:

COMPARATOR

INTERRUPT TIMING WITH

CMCON0 READ

Note 1: A write operation to the CMCON0 register

will also clear the mismatch condition

because

all

writes

include

read

operation at the beginning of the write

cycle.

2: Comparator

interrupts

will

operate

correctly regardless of the state of

CMOE.

Note 1: If a change in the CMCON0 register

(COUT) should occur when a read

operation is being executed (start of the

Q2 cycle), then the CMIF of the PIR1

2: When a comparator is first enabled, bias

circuitry in the comparator module may

cause

invalid

output

from

the

comparator until the bias circuitry is

stable. Allow about 1

s for bias settling

then clear the mismatch condition and

interrupt

flags

before

enabling

comparator interrupts.

CIN+

COUT

Set CMIF (edge)

CMIF

TRT

reset by software

CIN+

COUT

Set CMIF (edge)

CMIF

TRT

reset by software

cleared by CMCON0 read

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