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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AS3524 датащи(PDF) 27 Page - ams AG |
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AS3524 датащи(HTML) 27 Page - ams AG |
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27 / 124 page  AS3524 C21 / C22 austriamicrosystems Data Sheet, Confidential © 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11 27 - 124 5.2.6.4 IDE Interface Registers Table 13 IDE Interface Registers Register Name Base Address Offset Note IdeReg_BMICP AS3525_CF_IDE_BASE 0x00 primary channel bus master command IdeReg_BMISP AS3525_CF_IDE_BASE 0x02 primary channel bus master status IdeReg_BMIDTPP_LO AS3525_CF_IDE_BASE 0x04 primary channel bus master table pointer IdeReg_BMIDTPP_HI AS3525_CF_IDE_BASE 0x06 IdeReg_IDETIMP_LO AS3525_CF_IDE_BASE 0x40 primary channel timing register IdeReg_IDETIMP_HI AS3525_CF_IDE_BASE 0x41 IdeReg_IDETIMS_LO AS3525_CF_IDE_BASE 0x42 secondary channel timing register IdeReg_IDETIMS_HI AS3525_CF_IDE_BASE 0x43 IdeReg_SIDETIM AS3525_CF_IDE_BASE 0x44 slave IDE timing register IdeReg_SLEWCTL_LO AS3525_CF_IDE_BASE 0x45 slew rate control register IdeReg_SLEWCTL_HI AS3525_CF_IDE_BASE 0x46 IdeReg_IDESTAT AS3525_CF_IDE_BASE 0x47 IDE status register IdeReg_UDMACTL AS3525_CF_IDE_BASE 0x48 ultra DMA control register IdeReg_UDMATIM_LO AS3525_CF_IDE_BASE 0x4A ultra DMA timing register IdeReg_UDMATIM_HI AS3525_CF_IDE_BASE 0x4B IdeReg_MISCCTL AS3525_CF_IDE_BASE 0x50 miscellaneous control register IdeReg_REGSTB AS3525_CF_IDE_BASE 0x54 task file register strobe timing register IdeReg_REGRCVR AS3525_CF_IDE_BASE 0x58 task file register recovery timing register IdeReg_DATSTB AS3525_CF_IDE_BASE 0x5C data register PIO strobe timing register IdeReg_DATRCVR AS3525_CF_IDE_BASE 0x60 data register PIO recovery timing register IdeReg_DMASTB AS3525_CF_IDE_BASE 0x64 DMA strobe timing register IdeReg_DMARCVR AS3525_CF_IDE_BASE 0x68 DMA recovery timing register IdeReg_UDMASTB AS3525_CF_IDE_BASE 0x6C ultra DMA strobe timing register IdeReg_UDMATRP AS3525_CF_IDE_BASE 0x70 ultra DMA ready-to-stop timing register IdeReg_UDMATENV AS3525_CF_IDE_BASE 0x74 ultra DMA timing envelope register IdeReg_IORDYTMP AS3525_CF_IDE_BASE 0x78 primary IO ready timer configuration reg IdeReg_IORDYTMS AS3525_CF_IDE_BASE 0x7C secondary IO ready timer configuration reg IdeTaskF_DATA AS3525_CF_IDE_BASE 0x1F0 IdeTaskF_ERR_FEAT AS3525_CF_IDE_BASE 0x1F1 IdeTaskF_SECT_CNT AS3525_CF_IDE_BASE 0x1F2 IdeTaskF_SECT_NUM AS3525_CF_IDE_BASE 0x1F3 IdeTaskF_CYL_LO AS3525_CF_IDE_BASE 0x1F4 IdeTaskF_CYL_HI AS3525_CF_IDE_BASE 0x1F5 IdeTaskF_DEV_HEAD AS3525_CF_IDE_BASE 0x1F6 IdeTaskF_STAT_CMD AS3525_CF_IDE_BASE 0x1F7 IdeTaskF_ALT_STAT_DEV_CTRL AS3525_CF_IDE_BASE 0x3F6 IdeTaskF_DEV_ADDR AS3525_CF_IDE_BASE 0x3F7 |
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