AS3524 datasheet(90/124 Pages) AMSCO

90 / 124 page

AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.11

- 124

5.3.14 CGU - Clock generation unit

The clock generation unit generates all clocks for all modules on the chip.

• Hardware programmable selection of clock input either from internal oscillator or external clock input

• Two on-chip PLL circuits for generation of internal clocks

• Programmable divider for generation of ARM922T clock (fclk)

• Programmable divider for generation of AMBA bus clock (pclk)

• Support of ARM922T fastbus, synchronous and asynchronous mode

• Included clock gating registersto optimise power consumption

• Three clock busses at input of all dividers (clk_main, clk_a, clk_b) for utmost flexibility

• Spike-free switches between divider clock inputs (clk_main, clk_a, clk_b)

• Independent clock dividers for peripheral modules

System startup

At startup, the system is configured in a way to run without the need of PLLs. PLLs are disabled and clk_main is used for generation of the clock for

the ARM controller (fclk) and ARM AMBA bus (pclk). Within the clock gating register, only the clocks that are really necessary for initial boot are

enabled: clock for ARM, for the internal 1-TRAM memory, for the internal ROM and for the external memory. So the boot loader can start either

from internal ROM or from the external MPMC.

Clock switching

The system can be reconfigured to run from PLLA or PLLB. Because the 1-TRAM is a dynamic memory that must always get the clock for the

internal memory refresh, this switching must be implemented in a way that the PCLK clock is never stopped. The easiest solution to fulfil this

requirement is always switching back to clk_main for reconfiguring the PLLs. After reprogramming of the PLLs it must be checked that the PLLs are

locked before the system is switched onto the PLL output frequency.

ARM922T and AMBA bus clock

The ARM processor can run in different modes. These modes can be set within the iA, nF bits of the ARM922T CP15 (coprocessor) register 1.

Fastbus mode

This is the default mode after startup. The ARM922T input clock frequency is the same as the AHB/APB bus frequency.

Synchronous mode

Within the synchronous mode, the ARM922T frequency must be higher than the AHB/APB bus frequency and it must be an integer multiple of the

AHB/APB bus frequency. Advantage of the synchronous mode is a higher performance because of less synchronisation effort between the

ARM922T and the AHB bus.

Asynchronous mode

Within asynchronous mode, the ARM922T frequency must be higher than the AHB bus frequency, but it can be completely asynchronous.

Disatvantage is a slightly reduced performance of the system because of the higher effort for synchronisation between the ARM922T and AHB

clock domains.

Block Diagram

The block diagram on the following page gives a detailed view of the structure of the CGU.

AS3524 датащи(PDF) 90 Page - ams AG