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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AS3524 датащи(PDF) 73 Page - ams AG |
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AS3524 датащи(HTML) 73 Page - ams AG |
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73 / 124 page  AS3524 C21 / C22 austriamicrosystems Data Sheet, Confidential © 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11 73 - 124 5.3.12 DBOP - Data Block Output Port Purpose of this ARM APB peripheral module is a high-speed data output port that can support data transfer to various display controllers based on synchronous control interfaces. Programmability of polarity and timing of the generated control signals makes it possible to support various kinds of displays. Example of a supported display controller is the Hitachi HD77766R LCDE controller. From the programmers point of view the DBOP module can be serviced by DMA accesses. With the large size of the data FIFO and the programmable interrupt request conditions the overhead for SW is minimised. Simple read instructions to read for example a status register of the LCD controller are also supported. The usage of this cell results in a great performance boost compared to the standard ARM GPIO PrimeCell™ architecture. Features • APB bus interface • support for direct memory access (DMA) • data output FIFO with 128 words (32 bit wide) • 8 or 16 bit parallel data output (configurable) • 4 control outputs - flexible programming of the signal waveforms with respect to polarity and timing • programmable even/odd control output generation • 8 or 16 bit parallel data input register with programmable read strobe • programmable conditions for interrupt generation based on FIFO flags • usage of FIFO for simple division of APB clock domain and output clock domain • programmable data output rate in range of 0.05 to 4 MHz • APB Clock & DBOP Clocks are synchronous. Figure 31 DBOP Block Diagram Amba APB Interface PRESETn PSEL PENABLE PWRITE PADDR[11:2] PWDATA[31:0] PRDATA[7:0] PCLK Register Block DMA Interface DBOPDMASREQ DBOPDMABREQ DBOPDMACLR symetric FiFo Controller 32 32 Control Signal Generator dbop_clk c0 / xpb[0] c1 / xpb[1] c2 / xpb[2] c3 / xpb[3] dbop_d[7:0] / xpc[7:0] Din register FiFo push status FiFo pop status dinStrobe din[7:0] Interrupt Generator 8 dataValid Dout register lb_select, hb_select pop push Dual ported RAM 128x32 FiFo 128x32 DBOPIRQ DBOP dbop_d[11:8] / xpb[7:4] dbop_d[15:12] |
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