ADE7878 datasheet(80/92 Pages) AD

80 / 92 page

ADE7878

Rev. 0| Page 80 of 92

Bit

Location

Bit Name

Default Value

Description

REVAPA

When this bit is set to 1, it enables an interrupt when the Phase A active power identified by Bit 6

(REVAPSEL) in the ACCMODE[7:0] register (total or fundamental) changes sign.

REVAPB

When this bit is set to 1, it enables an interrupt when the Phase B active power identified by Bit 6

(REVAPSEL) in the ACCMODE[7:0] register (total or fundamental) changes sign.

REVAPC

When this bit is set to 1, it enables an interrupt when the Phase C active power identified by Bit 6

(REVAPSEL) in the ACCMODE[7:0] register (total or fundamental) changes sign.

REVPSUM1

When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF1

datapath changes sign.

REVRPA

When this bit is set to 1, it enables an interrupt when the Phase A reactive power identified by Bit

7 (REVRPSEL) in the ACCMODE[7:0] register (total or fundamental) changes sign.

REVRPB

When this bit is set to 1, it enables an interrupt when the Phase B reactive power identified by

Bit 7 (REVRPSEL) in the ACCMODE[7:0] register (total or fundamental) changes sign.

REVRPC

When this bit is set to 1, it enables an interrupt when the Phase C reactive power identified by

Bit 7 (REVRPSEL) in the ACCMODE[7:0] register (total or fundamental) changes sign.

REVPSUM2

When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF2

datapath changes sign.

CF1

When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs at the CF1

pin, that is an active low pulse is generated. The interrupt can be enabled even if the CF1 output

is disabled by setting Bit 9 (CF1DIS) to 1 in the CFMODE[15:0] register. The type of power used at

the CF1 pin is determined by Bits[2:0] (CF1SEL) in the CFMODE[15:0] register (see Table 39).

CF2

When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs at CF2 pin,

that is an active low pulse is generated. The interrupt may be enabled even if the CF2 output is

disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE[15:0] register. The type of power used at

the CF2 pin is determined by Bits[5:3] (CF2SEL) in the CFMODE[15:0] register (see Table 39).

CF3

When this bit is set to 1, it enables an interrupt when a high to low transition occurs at CF3 pin,

that is an active low pulse is generated. The interrupt may be enabled even if the CF3 output is

disabled by setting Bit 11 (CF3DIS) to 1 in the CFMODE[15:0] register. The type of power used at

the CF3 pin is determined by Bits[8:6] (CF3SEL) in the CFMODE[15:0] register (see Table 39).

DREADY

When this bit is set to 1, it enables an interrupt when all periodic (at 8 kHz rate) DSP

computations finish.

REVPSUM3

When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF3

datapath changes sign.

31:19

Reserved

00 0000 0000

0000

Reserved. These bits do not manage any functionality.

Table 34. MASK1 Register (Address 0xE50B)

Bit

Location

Bit Name

Default Value

Description

NLOAD

When this bit is set to 1, it enables an interrupt when at least one phase enters no load condition

based on total active and reactive powers.

FNLOAD

When this bit is set to 1, it enables an interrupt when at least one phase enters no load condition

based on fundamental active and reactive powers.

VANLOAD

When this bit is set to 1, it enables an interrupt when at least one phase enters no load condition

based on apparent power.

ZXTOVA

When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase A voltage is

missing.

ZXTOVB

When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase B voltage is

missing.

ZXTOVC

When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase C voltage is

missing.

ZXTOIA

When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase A current is

missing.

ADE7878 датащи(PDF) 80 Page - Analog Devices

ADE7878 датащи(HTML) 80 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

датащи скачать

ссылки URL