ADE7878 datasheet(78/92 Pages) AD

78 / 92 page

ADE7878

Rev. 0| Page 78 of 92

Bit

Location

Bit Name

Default Value

Description

REVAPB

When this bit is set to 1, it indicates that the Phase B active power identified by Bit 6

(REVAPSEL) in the ACCMODE[7:0] register (total or fundamental) has changed sign. The sign

itself is indicated in Bit 1 (BWSIGN) of the PHSIGN[15:0] register (see Table 41).

REVAPC

When this bit is set to 1, it indicates that the Phase C active power identified by Bit 6

(REVAPSEL) in the ACCMODE[7:0] register (total or fundamental) has changed sign. The sign

itself is indicated in Bit 2 (CWSIGN) of the PHSIGN[15:0] register (see Table 41).

REVPSUM1

When this bit is set to 1, it indicates that the sum of all phase powers in the CF1 datapath has

changed sign. The sign itself is indicated in Bit 3 (SUM1SIGN) of the PHSIGN[15:0] register (see

Table 41).

REVRPA

When this bit is set to 1, it indicates that the Phase A reactive power identified by Bit 7

(REVRPSEL) in the ACCMODE[7:0] register (total or fundamental) has changed sign. The sign

itself is indicated in Bit 4 (AVARSIGN) of the PHSIGN[15:0] register (see Table 41).

REVRPB

When this bit is set to 1, it indicates that the Phase B reactive power identified by Bit 7

(REVRPSEL) in the ACCMODE[7:0] register (total or fundamental) has changed sign. The sign

itself is indicated in Bit 5 (BVARSIGN) of the PHSIGN[15:0] register (see Table 41).

REVRPC

When this bit is set to 1, it indicates that the Phase C reactive power identified by Bit 7

(REVRPSEL) in the ACCMODE[7:0] register (total or fundamental) has changed sign. The sign

itself is indicated in Bit 6 (CVARSIGN) of the PHSIGN[15:0] register (see Table 41).

REVPSUM2

When this bit is set to 1, it indicates that the sum of all phase powers in the CF2 datapath has

changed sign. The sign itself is indicated in Bit 7 (SUM2SIGN) of the PHSIGN[15:0] register (see

Table 41).

CF1

When this bit is set to 1, it indicates that a high to low transition has occurred at CF1 pin; that

is, an active low pulse has been generated. The bit is set even if the CF1 output is disabled by

setting Bit 9 (CF1DIS) to 1 in the CFMODE[15:0] register. The type of power used at the CF1

pin is determined by Bits[2:0] (CF1SEL) in the CFMODE[15:0] register (see Table 39).

CF2

When this bit is set to 1, it indicates that a high-to-low transition has occurred at the CF2 pin;

that is, an active low pulse has been generated. The bit is set even if the CF2 output is

disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE[15:0] register. The type of power used

at the CF2 pin is determined by Bits[5:3] (CF2SEL) in the CFMODE[15:0] register (see Table 39).

CF3

When this bit is set to 1, it indicates that a high-to-low transition has occurred at CF3 pin; that

is, an active low pulse has been generated. The bit is set even if the CF3 output is disabled by

setting Bit 11 (CF3DIS) to 1 in the CFMODE[15:0] register. The type of power used at the CF3

pin is determined by Bits[8:6] (CF3SEL) in the CFMODE[15:0] register (see Table 39).

DREADY

When this bit is set to 1, it indicates that all periodical (at 8 kHz rate) DSP computations have

finished.

REVPSUM3

When this bit is set to 1, it indicates that the sum of all phase powers in the CF3 datapath has

changed sign. The sign itself is indicated in Bit 8 (SUM3SIGN) of the PHSIGN[15:0] register (see

Table 41).

31:19

Reserved

0 0000 0000 0000

Reserved. These bits are always 0.

Table 32. STATUS1 Register (Address 0xE503)

Bit

Location

Bit Name

Default Value

Description

NLOAD

When this bit is set to 1, it indicates that at least one phase entered no load condition based

on total active and reactive powers. The phase is indicated in Bits[2:0] (NLPHASE) in the

PHNOLOAD[15:0] register (see Table 36.)

FNLOAD

When this bit is set to 1, it indicates that at least one phase entered no load condition based

on fundamental active and reactive powers. The phase is indicated in Bits[5:3] (FNLPHASE) in

PHNOLOAD[15:0] register (see Table 36 in which this register is described).

VANLOAD

When this bit is set to 1, it indicates that at least one phase entered no load condition based

on apparent power. The phase is indicated in Bits[8:6] (VANLPHASE) in the PHNOLOAD[15:0]

ZXTOVA

When this bit is set to 1, it indicates that a zero crossing on Phase A voltage is missing.

ZXTOVB

When this bit is set to 1, it indicates that a zero crossing on Phase B voltage is missing.

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