ADE7878 datasheet(54/92 Pages) AD

54 / 92 page

ADE7878

Rev. 0 | Page 54 of 92

where:

n is the discrete time sample number.

T is the sample period.

In the ADE7878, the phase apparent powers are accumulated in

the AVAHR[31:0], BVAHR[31:0], and CVAHR[31:0] 32-bit

signed registers. The apparent energy register content can roll

over to full-scale negative (0x80000000) and continue increasing

in value when the apparent power is positive. Conversely, if

because of offset compensation in the rms datapath, the apparent

power is negative, the energy register underflows to full-scale

positive (0x7FFFFFFF) and continues to decrease in value.

Bit 4 (VAEHF) in the STATUS0[31:0] register is set when Bit 30

of one of the xVAHR registers changes, signifying that one of

these registers is half full. Because the apparent power is always

positive and the xVAHR registers are signed, the VA-hour registers

become half full when they increment from 0x3FFFFFFF to

0x4000 0000. Interrupts attached to Bit VAEHF in the

STATUS0[31:0] register can be enabled by setting Bit 4 in the

MASK0[31:0] register. If enabled, the IRQ0 pin is set low and

the status bit is set to 1 whenever one of the Energy Registers

xVAHR becomes half full. The status bit is cleared and the IRQ0

pin is set to high by writing to the STATUS0 register with the

corresponding bit set to 1.

Setting Bit 6 (RSTREAD) of the LCYMODE[7:0] register

enables a read-with-reset for all xVAHR accumulation registers;

that is, the registers are reset to 0 after a read operation.

Integration Time Under Steady Load

The discrete time sample period for the accumulation register is

125 μs (8 kHz frequency). With full-scale pure sinusoidal signals

on the analog inputs, the average word value representing the

apparent power is PMAX. If the VATHR threshold register is set

at the PMAX level, this means the DSP generates a pulse that is

added at the xVAHR registers every 125 μs.

The maximum value that can be stored in the xVAHR

accumulation register before it overflows is 231 − 1 or

0x7FFFFFFF. The integration time is calculated as

Time = 0x7FFF,FFFF × 125 μs = 74 hr 33 min 55 sec

(45)

Energy Accumulation Mode

The apparent power accumulated in each accumulation register

depends on the configuration of Bits[5:4] (CONSEL) in the

ACCMODE[7:0] register. The various configurations are

described in Table 19.

Table 19. Inputs to VA-Hour Accumulation Registers

CONSEL[1,0]

AVAHR

BVAHR

CVAHR

AVRMS × AIRMS

BVRMS × BIRMS

CVRMS × CIRMS

AVRMS × AIRMS

CVRMS × CIRMS

AVRMS × AIRMS

BVRMS × BIRMS

CVRMS × CIRMS

VB = −VA − VC

AVRMS × AIRMS

BVRMS × BIRMS

CVRMS × CIRMS

VB = −VA

Line Cycle Apparent Energy Accumulation Mode

As described in the Line Cycle Active Energy Accumulation

Mode section, in line cycle energy accumulation mode, the

energy accumulation can be synchronized to the voltage channel

zero crossings allowing apparent energy to be accumulated over an

integral number of half-line cycles. In this mode, the ADE7878

transfers the apparent energy accumulated in the 32-bit internal

accumulation registers into xVAHR[31:0] registers after an

integral number of line cycles, as shown in Figure 68. The

number of half-line cycles is specified in the LINECYC[15:0]

ZERO-

CROSSING

DETECTION

(PHASE A)

ZERO-

CROSSING

DETECTION

(PHASE B)

CALIBRATION

CONTROL

ZERO-

CROSSING

DETECTION

(PHASE C)

LINECYC[15:0]

AVAHR[31:0]

ZXSEL[0] IN

LCYCMODE[7:0]

ZXSEL[1] IN

LCYCMODE[7:0]

ZXSEL[2] IN

LCYCMODE[7:0]

AVAGAIN

AIRMS

AVRMS

ACCUMULATOR

VAHR[47:0]

32-BIT

Figure 68. Line Cycle Apparent Energy Accumulation Mode

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