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33899 датащи(PDF) 9 Page - Freescale Semiconductor, Inc |
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33899 датащи(HTML) 9 Page - Freescale Semiconductor, Inc |
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9 / 26 page ![]() Analog Integrated Circuit Device Data Freescale Semiconductor 9 33899 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics at -40 °C ≤ TA ≤ 125°C, 4.75V ≤ VCC ≤ 5.25V, 6.0V ≤ VIGNP ≤ 26.5V, unless otherwise noted. Typical values reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit PWM Frequency(8) fPWM – – 11 kHz PWM/Output Duty Cycle Accuracy Frequency = 10kHz, RS = 10k Ω, Slew Time = 1X, Duty cycle = 50% OUTACC -4.5 – 4.5 % Short-circuit Filter (S0 and S1) tSCF 4.0 – 11 μs Minimum PWM Low Pulse Width PWMMIN – – 0.2 μs Low Side Comparator One Shot Pulse Duration After a Low Side Comparator Trip tLSC 5.0 – 10 μs Low Side Comparator Blank Time Blanking Time After a Low Side Comparator Pulse(9) tLSCB 5.0 – 10 μs Over-temperature Shutdown Filter (time before Die Temp bit is set)(8) tOTF 5.0 – 13.5 μs Enable Lead Time(8) tLEAD 140 – – ns Enable Lag Time(8) tLAG 50 – – ns Delay Until Output Shuts OFF Short-circuit Detection or EN1 Falling or EN2 Falling Until H-Bridge Disables tSODLY – – 6.0 μs Delay Until Output Turns ON EN1 rising or EN2 rising Until H-Bridge Enables tENDLY – – 5.0 μs Dead Timer(9) Time Between High Side MOSFET and Low Side MOSFET Transition tDEAD 1.0 – 3.0 μs Open Load Fault Delay Duration of Fault Condition Until Fault Gets Latched In tFDO 175 – 400 μs Over-voltage Shutdown Filter Time from VIGNP > VOV to MOSFET Output Disable tOVS 100 – 200 μs Sleep Recovery Time(8),(9),(10) tSLEEP – 150 – μs Slew Time S0 and S1(11) (Output Load = 5.0mH and 1.6 Ω, 30% to 70%, VIGNP = 14.5V) Slew Mode = 1X RS= 50k Ω RS = 10k Ω, Short Slew Mode = 2X RS = 50k Ω RS = 10k Ω, Short Slew Mode = 4X RS = 50k Ω RS = 10k Ω, Short S0/S1RS 1.6 0.2 2.8 0.5 5.0 1.2 – – – – – – 3.2 0.8 6.3 1.5 12.8 3.0 μs Notes 8. Design information 9. Guaranteed by characterization, not production tested. 10. Sleep recovery time is the time from EN going high until the outputs are ready to respond to input. This time is dependent on the recovery time of VCCL and VCCL_POR. The recommended value for the VCCL capacitor is designed to permit initialization of internal logic prior to clearing of the POR condition (See +3.3V Input (VCCL) on page 12). 11. By design, if the RS input is left open, the slew time is the same as when shorted to GND. However, this is a high-impedance input and will be susceptible to external noise sources unless terminated appropriately. It is highly recommended to terminate this pin with either a ground or one of the program resistors . |
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