ATmega328P datasheet(271/448 Pages) ATMEL

271 / 448 page

271

8161D–AVR–10/09

ATmega48PA/88PA/168PA/328P

25.2.1

EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the

Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It

is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies

that the bit is cleared before writing to the SPMCSR Register.

25.2.2

Reading the Fuse and Lock Bits from Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the

Z-pointer with 0x0001 and set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM

instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are set

in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET

and SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM

instruction is executed within three CPU cycles or no SPM instruction is executed within four

CPU cycles. When BLBSET and SELFPRGEN are cleared, LPM will work as described in the

Instruction set Manual.

The algorithm for reading the Fuse Low byte is similar to the one described above for reading

the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET

and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles

after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse Low byte

(FLB) will be loaded in the destination register as shown below.See Table 27-5 on page 296 for

a detailed description and mapping of the Fuse Low byte.

Similarly, when reading the Fuse High byte (FHB), load 0x0003 in the Z-pointer. When an LPM

instruction is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the

SPMCSR, the value of the Fuse High byte will be loaded in the destination register as shown

below. See Table 27-5 on page 296 for detailed description and mapping of the Extended Fuse

byte.

Similarly, when reading the Extended Fuse byte (EFB), load 0x0002 in the Z-pointer. When an

LPM instruction is executed within three cycles after the BLBSET and SELFPRGEN bits are set

in the SPMCSR, the value of the Extended Fuse byte will be loaded in the destination register as

shown below. See Table 27-5 on page 296 for detailed description and mapping of the Extended

Fuse byte.

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are

unprogrammed, will be read as one.

Bit

76543210

––––––

LB2

LB1

Bit

321

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

Bit

765

321

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

Bit

321

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

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