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ATmega328P датащи(PDF) 249 Page - ATMEL Corporation |
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ATmega328P датащи(HTML) 249 Page - ATMEL Corporation |
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249 / 448 page ![]() 249 8161D–AVR–10/09 ATmega48PA/88PA/168PA/328P 22.3.3 DIDR1 – Digital Input Disable Register 1 • Bit 7..2 – Res: Reserved Bits These bits are unused bits in the ATmega48PA/88PA/168PA/328P, and will always read as zero. • Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corre- sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ- ten logic one to reduce power consumption in the digital input buffer. Bit 7 65 43 21 0 (0x7F) –– –– –– AIN1D AIN0D DIDR1 Read/Write RR RR RR R/W R/W Initial Value 0 00 00 00 0 |
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