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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATmega328P датащи(PDF) 198 Page - ATMEL Corporation |
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ATmega328P датащи(HTML) 198 Page - ATMEL Corporation |
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198 / 448 page  198 8161D–AVR–10/09 ATmega48PA/88PA/168PA/328P • Bits 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPMn setting. If a mismatch is detected, the UPEn Flag in UCSRnA will be set. • Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. • Bit 2:1 – UCSZn1:0: Character Size The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (Character SiZe) in a frame the Receiver and Transmitter use. • Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and the synchronous clock (XCKn). Table 19-5. UPMn Bits Settings UPMn1 UPMn0 Parity Mode 00 Disabled 01 Reserved 1 0 Enabled, Even Parity 1 1 Enabled, Odd Parity Table 19-6. USBS Bit Settings USBSn Stop Bit(s) 01-bit 12-bit Table 19-7. UCSZn Bits Settings UCSZn2 UCSZn1 UCSZn0 Character Size 00 0 5-bit 00 1 6-bit 01 0 7-bit 01 1 8-bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 11 1 9-bit |
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