ATmega32HVB datasheet(207/273 Pages) ATMEL

207 / 273 page

207

8042A–AVR–07/09

ATmega16HVB/32HVB

An LPM instruction within three cycles after LBSET and SPMEN are set in the SPMCSR Regis-

ter, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the

destination register. See ”Reading the Fuse and Lock Bits” on page 224 for details.

• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles executes Page Write, with the data stored in the temporary buffer. The page address is

taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit

will auto-clear upon completion of a Page Write, or after six cycles if no SPM instruction is exe-

cuted within four clock cycles. The CPU is halted during the entire Page Write operation if the

NRWW section is addressed.

• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The

data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase,

or after six cycles if no SPM instruction is executed within four clock cycles. The CPU is halted

during the entire Page Write operation if the NRWW section is addressed.

• Bit 0 – SPMEN: Store Program Memory Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one together with

either RWWSRE, LBSET, PGWRT’ or PGERS, the following SPM instruction will have a special

meaning, see description above. If only SPMEN is written, the following SPM instruction will

store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of

the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction,

or after six cycles if no SPM instruction is executed within four clock cycles. During Page Erase

and Page Write, the SPMEN bit remains high until the operation is completed.

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