ATmega32HVB datasheet(206/273 Pages) ATMEL

206 / 273 page

206

8042A–AVR–07/09

ATmega16HVB/32HVB

Note:

1. Z0: should be zero for all SPM commands, byte select for the LPM instruction.

See ”Addressing the Flash During Self-Programming” on page 196 for details about the use of

Z-pointer during Self-Programming.

29.9

29.9.1

SPMCSR – Store Program Memory Control and Status Register

The Store Program Memory Control and Status Register contains the control bits needed to con-

trol the Boot Loader operations.

• Bit 7 – SPMIE: SPM Interrupt Enable

When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM

ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN

bit in the SPMCSR Register is cleared.

• Bit 6 – RWWSB: Read-While-Write Section Busy

When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initi-

ated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section

cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a

Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be

cleared if a page load operation is initiated.

• Bit 5 - SIGRD: Signature Row Read

If this bit is written to one at the same time as SPMEN, the next LPM instruction within three

clock cycles will read a byte from the signature row into the destination register. See”Reading

the Signature Row from Software” on page 199 for details.

An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect. This

operation is reserved for future use and should not be used.

• Bit 4 – RWWSRE: Read-While-Write Section Read Enable

When programming (Page Erase or Page Write) to the RWW section, the RWW section is

blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the

user software must wait until the programming is completed (SPMEN will be cleared). Then, if

the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within

four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while

the Flash is busy with a Page Erase or a Page Write (SPMEN is set). If the RWWSRE bit is writ-

ten while the Flash is being loaded, the Flash load operation will abort and the data loaded will

be lost.

• Bit 3 – LBSET: Lock Bit Set

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles sets Lock bits, according to the data in R0. The data in R1 and the address in the Z-

pointer are ignored. The LBSET bit will automatically be cleared upon completion of the Lock bit

set, or after six cycles if no SPM instruction is executed within four clock cycles.

Bit

0x37 (0x57)

SPMIE

RWWSB

SIGRD

RWWSRE

LBSET

PGWRT

PGERS

SPMEN

SPMCSR

Read/Write

R/W

Initial Value

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