ATmega32HVB datasheet(143/273 Pages) ATMEL

143 / 273 page

143

8042A–AVR–07/09

ATmega16HVB/32HVB

Notes:

1. The actual value depends on the actual frequency of the ”Ultra Low Power RC Oscillator” on

page 27. See ”Electrical Characteristics” on page 228.

2. Initial value.

3. An additional delay Td can be expected after enabling the corresponding FET. This is related to

the initialization of the protection circuitry. For the Discharge Over-Current protection, this

applies when enabling the Discharge FET. For Charge Over-Current protection, this applies

when enabling the Charge FET. With nominal ULP frequency this delay is maximum 0.1 ms.

Note:

Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator

cycles + 3 CPU clock cycles is required between each time the BPOCTR register is written. Any

writing to the BPOCTR register during this period will be ignored.

24.7.5

BPHCTR – Battery Protection High-current Timing Register

• Bit 7:6 – Res: Reserved Bits

These bits are reserved in the ATmega16HVB/32HVB and will always read as zero.

• Bit 5:0 – HCPT5:0: High-current Protection Timing

These bits control the delay of the High-circuit Protection. The High-current Timing can be set

with a step size of 2 ms as shown in Table 24-4 on page 143.

Table 24-3.

Over-current Protection Reaction Time. OCPT[5:0] with corresponding Over-cur-

rent Delay Time.

Over-current Protection Reaction Time(1)

OCPT[5:0]

Typ

0x00

(0.0 - 0.5 ms) + T

(3)

0x01

(0.0 - 0.5 ms) + Td

(3)

0x02(2)

(0.5 - 1.0 ms) + Td

(3)

0x03

(1.0 - 1.5 ms) + T

(3)

...

0x3E

(30.5 - 31.0 ms) + Td

(3)

0x3F

(31.0 - 31.5 ms) + T

(3)

Bit

765

432

(0xFC)

–

HCPT[5:0]

BPHCTR

Read/Write

R/W

Initial Value

Table 24-4.

High-current Protection Reaction Time. HCPT[5:0] with corresponding High-cur-

rent Delay Time.

High-current Protection Reaction Time(1)

HCPT[5:0]

Typ

0x00

(0 - 2 ms) + Td

(3)

0x01(2)

(0 - 2 ms) + Td

(3)

0x02

(2 - 4 ms) + T

(3)

0x03

(4 - 6 ms) + Td

(3)

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