ATmega32HVB datasheet(133/273 Pages) ATMEL

133 / 273 page

133

8042A–AVR–07/09

ATmega16HVB/32HVB

23.3

Regulator Start-up

When the chip is in power-off mode the Voltage Regulator will be off and there will be no con-

nection between VFET and VREG.

The regulator is started when the Charger Detect module detects that a charger is connected

(For details on Charger Detect, see ”Charger Detect” on page 129). When starting the regulator

the Voltage Regulator will stay in a force mode where the VREG output is raised against the

VFET input voltage. As VREG increases to the target voltage level the regulator will automati-

cally enter regulation mode, with a stable output voltage of nominally 3.3V. Figure 11-2 on page

44, in System Control and Reset illustrates the start-up sequence from power-off.

23.4

Battery Pack Short Detection

The Voltage Regulator will continuously monitor the operating condition at the VFET terminal. If

the voltage at VFET drops below the Regulator Short-circuit Level (RSCL), see ”Electrical Char-

acteristics” on page 228, the Voltage Regulator enters the Battery Pack Short mode. In this

mode, VFET is disconnected from VREG to avoid a quick drop in the voltage regulator output.

When the voltage regulator enters this mode, the chip will be completely powered by the exter-

nal reservoir capacitor (CREG). This allows the chip to operate a certain time without entering

BOD reset, even if the VFET voltage is too low for the voltage regulator to operate.

An interrupt is issued when the regulator enters Battery Pack Short mode, if the ROCWIE bit in

ROCR Register is set. This allows actions to be taken to reduce power consumption and hence

prolonging the time that CREG can be used to power the chip.

In a typical short-circuit situation, VFET will drop as a consequence of high current consumption,

and recover as soon as the Battery Protection module has disabled the FETs. Hence CREG

should be dimensioned so that the chip can sustain operation without entering BOD reset, until

the FETs are disabled either by HW or SW.

To minimize power consumption when the Voltage Regulator enters the Battery Pack Short

mode, the chip should enter Power-save sleep mode as soon as possible after the ROCWIF

interrupt is detected. The Watchdog Timer should be configured to wake up the CPU after a time

that is considered safe, see application note AVR132 for use of enhanced Watchdog Timer.

Software should then check the status of the ROC flag. If the ROCS flag is cleared, normal oper-

ation may be resumed.

23.5

Black-Out Detection

To ensure that the internal logic has safe operating condition, the Voltage Regulator has built-in

Black-Out Detector (BLOD). If the voltage at the VREG pin drops below the Black-out Detection

Level, V

BLOT, the chip will automatically enter Power-off mode.

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