ATmega325P datasheet(299/364 Pages) ATMEL

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8023F–AVR–07/09

ATmega325P/3250P

Figure 25-16. State Machine Sequence for Changing/Reading the Data Word

25.8.11

Flash Data Byte Register

The Flash Data Byte Register provides an efficient way to load the entire Flash page buffer

before executing Page Write, or to read out/verify the content of the Flash. A state machine sets

up the control signals to the Flash and senses the strobe signals from the Flash, thus only the

data words need to be shifted in/out.

The Flash Data Byte Register actually consists of the 8-bit scan chain and a 8-bit temporary reg-

ister. During page load, the Update-DR state copies the content of the scan chain over to the

temporary register and initiates a write sequence that within 11 TCK cycles loads the content of

the temporary register into the Flash page buffer. The AVR automatically alternates between

writing the low and the high byte for each new Update-DR state, starting with the low byte for the

first Update-DR encountered after entering the PROG_PAGELOAD command. The Program

Counter is pre-incremented before writing the low byte, except for the first written byte. This

ensures that the first data is written to the address set up by PROG_COMMANDS, and loading

the last location in the page buffer does not make the Program Counter increment into the next

page.

During Page Read, the content of the selected Flash byte is captured into the Flash Data Byte

low and the high byte for each new Capture-DR state, starting with the low byte for the first Cap-

Test-Logic-Reset

Run-Test/Idle

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Select-IR Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Select-DR Scan

Capture-DR

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