ATmega325P datasheet(265/364 Pages) ATMEL

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265

8023F–AVR–07/09

ATmega325P/3250P

When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM instruction

is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the

value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown below.

Refer to Table 25-3 on page 272 for detailed description and mapping of the Extended Fuse

byte.

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are

unprogrammed, will be read as one.

24.8.10

Preventing Flash Corruption

During periods of low V

CC, the Flash program can be corrupted because the supply voltage is

too low for the CPU and the Flash to operate properly. These issues are the same as for board

level systems using the Flash, and the same design solutions should be applied.

A Flash program corruption can be caused by two situations when the voltage is too low. First, a

regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,

the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions

is too low.

Flash corruption can easily be avoided by following these design recommendations (one is

sufficient):

If there is no need for a Boot Loader update in the system, program the Boot Loader Lock

bits to prevent any Boot Loader software updates.

Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done by enabling the internal Brown-out Detector (BOD) if the operating volt-

age matches the detection level. If not, an external low V

CC reset protection circuit can be

used. If a reset occurs while a write operation is in progress, the write operation will be

completed provided that the power supply voltage is sufficient.

Keep the AVR core in Power-down sleep mode during periods of low V

CC. This will pre-

vent the CPU from attempting to decode and execute instructions, effectively protecting

the SPMCSR Register and thus the Flash from unintentional writes.

24.8.11

Programming Time for Flash when Using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 24-5 shows the typical pro-

gramming time for Flash accesses from the CPU.

Note:

1. Minimum and maximum programming time is per individual operation.

Bit

765

3210

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

Bit

765

3210

–

EFB2

EFB1

EFB0

Table 24-5.

SPM Programming Time(1)

Symbol

Min Programming Time

Max Programming Time

Flash write (Page Erase, Page Write, and

write Lock bits by SPM)

3.7 ms

4.5 ms

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