ATmega325P datasheet(264/364 Pages) ATMEL

264 / 364 page

264

8023F–AVR–07/09

ATmega325P/3250P

RWWSB by writing the RWWSRE. See ”Simple Assembly Code Example for a Boot Loader” on

page 266 for an example.

24.8.7

Setting the Boot Loader Lock Bits by SPM

To set the Boot Loader Lock bits and general Lock bits, write the desired data to R0, write

“X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR.

See Table 24-2 and Table 24-3 for how the different settings of the Boot Loader bits affect the

Flash access.

If bits 5:0 in R0 are cleared (zero), the corresponding Lock bit will be programmed if an SPM

instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCSR. The Z-

pointer is don’t care during this operation, but for future compatibility it is recommended to load

the Z-pointer with 0x0001 (same as used for reading the Lock bits). For future compatibility it is

also recommended to set bits 7, and 6 in R0 to “1” when writing the Lock bits. When program-

ming the Lock bits the entire Flash can be read during the operation.

24.8.8

EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the

Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It

is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies

that the bit is cleared before writing to the SPMCSR Register.

24.8.9

Reading the Fuse and Lock Bits from Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the

Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruc-

tion is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR,

the value of the Lock bits will be loaded in the destination register. The BLBSET and SPMEN

bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed

within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLB-

SET and SPMEN are cleared, LPM will work as described in the Instruction set Manual.

The algorithm for reading the Fuse Low byte is similar to the one described above for reading

the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET

and SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the

BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be

loaded in the destination register as shown below. Refer to Table 25-5 on page 273 for a

detailed description and mapping of the Fuse Low byte.

Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc-

tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR,

the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below.

Refer to Table 25-4 on page 273 for detailed description and mapping of the Fuse High byte.

Bit

765

432

BLB12

BLB11

BLB02

BLB01

LB2

LB1

Bit

765

432

–

BLB12

BLB11

BLB02

BLB01

LB2

LB1

Bit

765

3210

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

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